參數(shù)資料
型號(hào)： ADMCF341BR
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： DashDSP⑩ 28-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End
中文描述： 0-BIT, 10 MHz, OTHER DSP, PDSO28
封裝： SOIC-28
文件頁(yè)數(shù)： 20/36頁(yè)
文件大?。?/td> 1106K
代理商： ADMCF341BR
REV. 0
–20–
ADMCF341
Each analog front end has two analog inputs: voltage and cur-
rent. A 2-to-1 multiplexer selects which input will be converted;
the multiplexer selection is determined by the MODECTRL
register. Note that in the ADMCF341 only the current inputs
(I
SENSE
) are externally available.
The current input (I
SENSE
) is amplified through a bipolar ampli-
fier (gain –2.5). There is an output offset that matches the
amplifier output signal range to the input signal range of the
A/D converter. The amplifier has built-in overcurrent and open-
circuit protection. The overcurrent protection shuts the PWM
Block when the voltage at any of the I
SENSE
pins exceeds the trip
threshold (high or low). The open-circuit detection shuts the
PWM block when any of the I
SENSE
inputs is in high impedance
(for example, the current sense resistor or transducer is discon-
nected). The shutdown signals generated by the amplifiers are
then OR-ed and filtered in order to avoid a spurious trip caused
by the switching of the power devices. The amplifier is followed
by a sample-and-hold amplifier (SHA). The SHA time is user-
programmable through the SHA timer register. The sampling
time is set as a delay from the rising edge of the PWMSYNC
signal and is calculated as:
=
(
The SHA timer counter has a minimum reload value of 0x0003,
which ensures a minimum settling time of the SHA output in
case the user is programming the SHA timer register to a value
smaller than 0x0003. This means that the sampling time is
programmable from 5 t
CK
to 65,535 t
CK
(corresponding to 250 ns
to 3.28 ms for a CLKOUT rate of 20 MHz). The sampling time
is limited, however, to the rising edge of the following PWMSYNC
cycle. Each channel has an independent amplifier, SHA, and
SHA timing unit/state machine. Figure 16 shows a conversion
sequence of a single channel.
At the beginning of the cycle N (rising edge of PWMSYNC
signal (1), the timer counter is loaded with the value contained
in the SHA_CNT register. After the timer counter has been
reloaded, it starts counting down at the CLKOUT rate. In this
phase the SHA state-machine forces the SHA in TRACK
(sample) status.
When the counter reaches the value of 0x0000 (after the time
T
SAMPLE
from the rising edge of PWMSYNC), the SHA state-
machine forces the SHA in HOLD status.
The conversion of the sampled value is then taking place in the
cycle N + 1 [from (4) to (5)] in Figure 16 and the result of the
conversion is available on the ADC register at the cycle N + 2
[rising edge of PWMSYNC (5)].
On cycle N + 2, the reload value of the timer counter exceeds
the period of the PWMSYNC signal. In this case the SHA state-
machine forces the SHA in HOLD status at the rising edge of
PWMSYNC of the next cycle (7). The conversion then takes place
on cycle N + 3, and the conversion result is available on the ADC
register at the cycle N + 4 [rising edge of PWMSYNC (9)].
T
SHA CNT
_
t
SAMPLE
CK
+
￥
)
2
During the acquire phase (the PWMSYNC cycle during the
sampling of the input value) the conversion takes place. How-
ever, the value on the ADC registers is not considered valid.
This condition is signaled by the ADC by setting the LSB of the
ADC register to high.
On cycle N + 4, at the rising edge of the PWMSYNC signal (9),
the timer counter is reloaded with a value smaller than the
PWMSYNC pulsewidth. In this case the SHA samples within
the PWMSYNC pulsewidth and the conversion takes place in
the same PWMSYNC cycle [from (10) to (11)].
AUXILIARY PWM TIMERS
Overview
The ADMCF341 provides two variable frequency, variable duty
cycle, 16-bit, auxiliary PWM outputs that, when enabled, are
available at the AUX1 and AUX0 pins. These auxiliary PWM
outputs can be used to provide switching signals to other
circuits in typical motor control systems, such as power factor
corrected front end converters or other switching power con-
verters. Alternatively, by adding a suitable filter network, the
auxiliary PWM output signals can be used as simple single-bit
digital-to-analog converters as shown in Figure 17. The auxiliary
PWM system of the ADMCF341 can operate in two different
modes: independent mode and offset mode. The operating
mode of the auxiliary PWM system is controlled by Bit 8 of the
MODECTRL register. Setting Bit 8 of the MODECTRL regis-
ter places the auxiliary PWM system in the independent mode.
In this mode, the two auxiliary PWM generators are completely
independent and separate switching frequencies and duty cycles
may be programmed for each auxiliary PWM output. In this
mode, the 16-bit AUXTM0 register sets the switching frequency
of the signal at the AUX0 output pin. Similarly, the 16-bit
AUXTM1 register sets the switching frequency of the signal at
the AUX1 pin. The fundamental time increment for the auxiliary
PWM outputs is twice the DSP instruction rate (or 2 t
CK
) and
the corresponding switching periods are given by:
T
AUXTM
T
AUXTM
AUX
1
2
=
￥
(
Since the values in both AUXTM0 and AUXTM1 can range
from 0 to 0xFFFF, the achievable switching frequency of the
auxiliary PWM signals may range from 152.59 Hz to 10 MHz
for a CLKOUT frequency of 20 MHz. The on-time of the two
auxiliary PWM signals is programmed by the two 16-bit
AUXCH0 and AUXCH1 registers, according to:
=
=
so that output duty cycles from 0% to 100% are possible. Duty
cycles of 100% are produced if the on-time value exceeds the
period value. Typical auxiliary PWM waveforms in independent
mode are shown in Figure 18a. When bit 8 of the MODECTRL
register is cleared, the auxiliary PWM channels are placed
t
t
AUX
CK
CK
0
2
0 1
1 1
=
￥
￥
￥
(
)
)
T
T
AUX
AUX
AUXCH
AUXCH
t
t
ON
CK
ON
CK
,
,
(
(
)
￥
)
0
1
2
2
0
1
￥
￥
￥
Table VIII. Fundamental Characteristics of Auxiliary PWM Timers
Parameter
Test Conditions
Min
Typ
Max
Unit
Resolution
PWM Frequency
16
Bits
MHz
10 MHz CLKIN
0.152
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