參數(shù)資料
型號(hào)： ADMCF341BR
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： DashDSP⑩ 28-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End
中文描述： 0-BIT, 10 MHz, OTHER DSP, PDSO28
封裝： SOIC-28
文件頁(yè)數(shù)： 12/36頁(yè)
文件大?。?/td> 1106K
代理商： ADMCF341BR
REV. 0
–12–
ADMCF341
The PWM generator is capable of operating in two distinct modes:
single update mode and double update mode. In single update
mode, the duty cycle values are programmable only once per
PWM period, so that the resultant PWM patterns are symmetrical
about the midpoint of the PWM period. In double update mode,
a second updating of the PWM duty cycle values is implemented
at the midpoint of the PWM period. In this mode, it is possible
to produce asymmetrical PWM patterns that produce lower
harmonic distortion in three-phase PWM inverters. This tech-
nique also permits the closed-loop controller to change the
average voltage applied to the machine winding at a faster rate,
allowing wider closed-loop bandwidths to be achieved. The
operating mode of the PWM block (single or double update
mode) is selected by a control bit in MODECTRL register.
The PWM generator of the ADMCF341 also provides an inter-
nal signal that synchronizes the PWM switching frequency to
the A/D operation. In single update mode, a PWMSYNC pulse
is produced at the start of each PWM period. In double update
mode, an additional PWMSYNC pulse is produced at the mid-
point of each PWM period. The width of the PWMSYNC pulse
is programmable through the PWMSYNCWT register.
The PWM signals produced by the ADMCF341 can be shut off
in a number of different ways. First, there is a dedicated asyn-
chronous PWM shutdown pin,
PWMTRIP
, which, when
brought LOW, instantaneously places all six PWM outputs in
the OFF state. In addition, PWM shutdown is initiated when
the voltage on any of the input pins (I
SENSE
) exceeds the trip
thresholds (high or low) or the input is unconnected (floating).
Because these two hardware shutdown mechanisms are asyn-
chronous, and the associated PWM disable circuitry does not
use clocked logic, the PWM will shut down even if the DSP
clock is not running. The PWM system may also be shut down
from software by writing to the PWMSWT register.
Status information about the PWM system of the ADMCF341
is available to the user in the SYSSTAT register. In particular,
the state of
PWMTRIP
is available, as well as a status bit that
indicates whether the operation is in the first half or the second
half of the PWM period.
A functional block diagram of the PWM controller is shown in
Figure 6. The generation of the six output PWM signals on pins
AH to CL is controlled by four important blocks:
∑
PWM controller, generates three pairs of complemented
and dead-time-adjusted center-based PWM signals.
∑
puts of the three-phase timing unit for each channel to
either the high side or the low side output. In addition, the
output control unit allows individual enabling/disabling of
each of the six PWM output signals.
∑
and its subsequent mixing with the PWM signals.
∑
shutdown modes (via the
PWMTRIP
pin, the analog block,
or the PWMSWT register) and generates the correct
RESET
signal for the timing unit.
The three-phase PWM timing unit, which is the core of the
The output control unit allows the redirection of the out-
The GATE drive unit provides the high chopping frequency
The PWM shutdown controller manages the three PWM
The PWM controller is driven by a clock at the same frequency
as the DSP instruction rate, CLKOUT, and is capable of gener-
ating two interrupts to the DSP core. One interrupt is generated
on the occurrence of a PWMSYNC pulse, and the other is
generated on the occurrence of any PWM shutdown action.
Three-Phase Timing Unit
The 16-bit three-phase timing unit is the core of the PWM
controller and produces three pairs of pulsewidth modulated
signals with high resolution and minimal processor overhead.
There are four main configuration registers (PWMTM,
PWMDT, PWMPD, and PWMSYNCWT) that determine the
fundamental characteristics of the PWM outputs. In addition,
the operating mode of the PWM (single or double update
mode) is selected by bit 6 of the MODECTRL register. These
registers, in conjunction with the three 16-bit duty cycle regis-
ters (PWMCHA, PWMCHB and PWMCHC), control the
output of the three-phase timing unit.
PWM Switching Frequency: PWMTM Register
The PWM switching frequency is controlled by the PWM
period register, PWMTM. The fundamental timing unit of
the PWM controller is t
CK
= 1/f
CLKOUT
, where f
CLKOUT
is the
CLKOUT frequency (DSP instruction rate). Therefore, for a
20 MHz CLKOUT, the fundamental time increment is 50 ns.
The value written to the PWMTM register is effectively the
number of t
CK
clock increments in half a PWM period. The
required PWMTM value is a function of the desired PWM
switching frequency (f
PWM
) and is given by:
PWMTM
f
f
f
f
CLKOUT
￥
PWM
CLKIN
PWM
=
=
2
Therefore, the
PWM
switching period, T
S
, can be written as:
T
PWMTM
t
S
CK
=
￥
￥
2
For example, for a 20 MHz CLKOUT and a desired PWM
switching frequency of 10 kHz (T
S
= 100
m
s), the correct value
to load into the PWMTM register is:
PWMTM
0x E
=
=
=
20 10
2 10 10
1000
6
3
The largest value that can be written to the 16-bit PWMTM
register is 0xFFFF = 65,535, which corresponds to a minimum
PWM switching frequency of:
f
Hz
PWM
,min
,
=
￥
=
20 10
2
65 535
153
6
for a CLKOUT frequency of 20 MHz.
PWM Switching Dead Time: PWMDT Register
The second important PWM block parameter that must be
initialized is the switching dead time. This is a short delay time
introduced between turning off one PWM signal (e.g., AH) and
turning on its complementary signal (e.g., AL). This short time
delay is introduced to permit the power switch being turned off
to completely recover its blocking capability before the comple-
mentary switch is turned on. This time delay prevents a
potentially destructive short-circuit condition from developing
across the dc link capacitor of a typical voltage source inverter.
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