參數(shù)資料
型號： ADMC401
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： Single-Chip, DSP-Based High Performance Motor Controller
中文描述： 24-BIT, 13 MHz, OTHER DSP, PQFP144
封裝： TQFP-144
文件頁數(shù)： 6/60頁
文件大小： 417K
代理商： ADMC401
REV. B
ADMC401
–6–
Parameter
Interrupts and Flags
Timing Requirements
:
t
IFS
t
IFH
Switching Characteristics
:
t
FOH
t
FOD
Min
Max
Unit
IRQx
or FI Setup before CLKOUT Low
1, 2, 3
IRQx
or FI Hold after CLKOUT High
1, 2, 3
0.25t
CK
+ 15
0.25t
CK
ns
ns
Flag Output Hold after CLKOUT Low
4
Flag Output Delay from CLKOUT Low
4
0.5t
CK
– 7
ns
ns
0.5t
CK
+ 5
NOTES
1
If
IRQx
and FI inputs meet t
and t
setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the
ADSP-2100 Family User’s Manual,
Third Edition for further
information on interrupt servicing.)
2
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx
=
IRQ0
and
IRQ1
.
4
Flag Output = FL1 and FO.
CLKOUT
FLAG
OUTPUTS
IRQ
x
FI
t
FOH
t
IFH
t
IFS
t
FOD
Figure 2. Interrupts and Flags
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