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參數(shù)資料
| 型號： | ADMC401 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Single-Chip, DSP-Based High Performance Motor Controller |
| 中文描述： | 24-BIT, 13 MHz, OTHER DSP, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 32/60頁 |
| 文件大小： | 417K |
| 代理商： | ADMC401 |
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REV. B
ADMC401
–32–
signals, setting Bit 7 enables crossover on the BH/BL pair of
PWM signals and setting Bit 6 enables crossover on the CH/CL
pair of PWM signals. If crossover mode is enabled for any pair
of PWM signals, the high side PWM signal from the timing unit
(AH say) is diverted to the associated low side output of the
Output Control Unit so that the signal will ultimately appear at
the AL pin. Of course, the corresponding low side output of the
Timing Unit is also diverted to the complementary high side
output of the Output Control Unit so that the signal appears at
the AH pin. Following a reset, the three crossover bits are cleared
so that the crossover mode is disabled on all three pairs of PWM
signals.
Output Enable Function
The PWMSEG register also contains six bits (Bits 0 to 5) that
can be used to individually enable or disable each of the six
PWM outputs. The PWM signal of the AL pin is enabled by
setting Bit 5 of the PWMSEG register while Bit 4 controls AH,
Bit 3 controls BL, Bit 2 controls BH, Bit 1 controls CL and Bit
0 controls the CH output. If the associated bit of the PWMSEG
register is set, the corresponding PWM output is disabled irre-
spective of the value of the corresponding duty cycle register.
This PWM output signal will remain in the OFF state as long as
the corresponding enable/disable bit of the PWMSEG register is
set. This output enable function is implemented after the cross-
over function. Following a reset, all six enable bits of the
PWMSEG register are cleared so that all PWM outputs are
enabled by default. In a manner identical to the duty cycle
registers, the PWMSEG is latched on the rising edge of the
PWMSYNC signal so that changes to this register only become
effective at the start of each PWM cycle in single update mode.
In double update mode, the PWMSEG register can also be
updated at the midpoint of the PWM cycle.
Brushless DC Motor (Electronically Commutated Motor)
Control
In the control of an ECM only two inverter legs are switched at
any time and often the high side device in one leg must be switched
ON at the same time as the low side driver in a second leg.
Therefore, by programming identical duty cycle values for two
PWM channels (i.e., PWMCHA = PWMCHB) and setting Bit 7
of the PWMSEG register to crossover the BH/BL pair of PWM
signals, it is possible to turn ON the high side switch of Phase A
and the low side switch of phase B at the same time. In the
control of ECM, it is usual that the third inverter leg (Phase C
in this example) be disabled for a number of PWM cycles. This
function is implemented by disabling both the CH and CL
PWM outputs by setting Bits 0 and 1 of the PWMSEG register.
This situation is illustrated in Figure 25, where it can be seen
that both the AH and BL signals are identical, since PWMCHA
= PWMCHB and the crossover bit for Phase B is set. In addi-
tion, the other four signals (AL, BH, CH and CL) have been
disabled by setting the appropriate enable/disable bits of the
PWMSEG register. For the situation illustrated in Figure 25,
the appropriate value for the PWMSEG register is 0x00A7. In
normal ECM operation, each inverter leg is disabled for certain
periods of time, so that the PWMSEG register is changed based
on the position of the rotor shaft (motor commutation).
AH
AL
BH
BL
CH
CL
PWMTM
PWMTM
PWMCHA
= PWMCHB
PWMCHA
= PWMCHB
2
PWMDT
2
PWMDT
Figure 25. Example active LO PWM signals suitable for
ECM control, PWMCHA = PWMCHB, crossover BH/BL pair
and disable AL, BH, CH and CL outputs. Operation is in
single update mode.
GATE DRIVE UNIT, PWMGATE REGISTER
High Frequency Chopping
The Gate Drive Unit of the PWM controller adds features that
simplify the design of isolated gate drive circuits for PWM invert-
ers. If a transformer-coupled power device gate drive amplifier is
used, the active PWM signal must be chopped at a high fre-
quency. The 10-bit PWMGATE register allows the program-
ming of this high frequency chopping mode. The chopped active
PWM signals may be required for the high-side drivers only, for
the low side drivers only or for both the high side and low side
switches. Therefore, independent control of this mode for both
high and low side switches is included with two separate control
bits in the PWMGATE register.
Typical PWM output signals with high frequency chopping
enabled on both high side and low side signals are shown in
Figure 26. Chopping of the high side PWM outputs (AH, BH
and CH) is enabled by setting Bit 8 of the PWMGATE register.
Chopping of the low side PWM outputs (AL, BL and CL) is
enabled by setting Bit 9 of the PWMGATE register. The high
frequency chopping frequency is controlled by the 8-bit word
(GDCLK) placed in Bits 0 to 7 of the PWMGATE register.
The period of this high frequency carrier is:
(
T
GDCLK
t
CHOP
CK
=
×
+
)
[
]
×
4
1
and the chopping frequency is therefore an integral subdivision
of the CLKOUT frequency:
f
f
GDCLK
(
CHOP
CLKOUT
=
×
+
)
[
]
4
1
The
GDCLK
value may range from 0 to 255, corresponding
to a programmable chopping frequency rate from 25.4 kHz to
6.5 MHz for a 26 MHz CLKOUT rate. The gate drive features
must be programmed before operation of the PWM controller
and typically are not changed during normal operation of the
PWM controller. Following reset, all bits of the PWMGATE
register are cleared so that high frequency chopping is disabled,
by default.
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