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參數(shù)資料
| 型號： | ADMC401 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Single-Chip, DSP-Based High Performance Motor Controller |
| 中文描述： | 24-BIT, 13 MHz, OTHER DSP, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 17/60頁 |
| 文件大小： | 417K |
| 代理商： | ADMC401 |
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ADMC401
–17–
REV. B
PIN FUNCTION DESCRIPTION
The ADMC401 is available in an 144-lead TQFP package. Table
I contains the pin descriptions.
Table I. Pin List
Pin
Group
Name
#
of
Pins Output Function
Input/
A13–A0
D23–D0
PMS
,
DMS
,
BMS
RD
,
WR
MMAP
POR
RESET
CLKOUT
CLKIN, XTAL
14
24
3
2
1
1
1
1
2
O
I/O
O
O
I
O
I
O
I, O
Address Lines
Data Lines
External Memory Select Lines
External Memory Read/Write Enable
Memory Map Select
Internal Power On Reset Output
Processor Reset Input
Processor Clock Output
External Clock or Quartz Crystal
Input
Bus Request
Bus Grant and Bus Hang Control
Boot Mode Select
Power-Down and Power-Down
Acknowledge
Serial Port 0 Pins (TFS0, RFS0,
DT0, DR0, SCLK0)
Serial Port 1 (TFS1/
IRQ1
, RFS1/
IRQ0
/
SROM
, DT1/FO, DR1A/FI,
DR1B/FI, SCLK1)
Analog Inputs
Inverting Inputs to Sample and
Hold Amplifiers
Analog Input for Gain Calibration
Reference Voltage Input/Output
Reference Common
Common-
Mode
Level (Midsupply)
Noise Reduction Pins
Voltage Reference Select
External Convert Start
PWM Outputs
PWM Shutdown Signal
PWM Polarity Control
PWM Synchronization Output
PWM Switched Reluctance Mode
Control
Digital I/O Port
Event Timer Inputs
Auxiliary PWM Outputs
BR
BG
,
BGH
BMODE
PWD
, PWDACK
1
2
1
2
I
O
I
I, O
SPORT0
5
I/O
SPORT1
6
I/O
VIN0–VIN7
ASHAN, BSHAN
8
2
I
I
GAIN
V
REF
REFCOM
CML
CAPT, CAPB
SENSE
CONVST
AH-CL
PWMTRIP
PWMPOL
PWMSYNC
PWMSR
1
1
1
1
2
1
1
6
1
1
1
1
I
I/O
GND
O
O
I
I
O
I
I
O
I
PIO0–PIO11
ETU0, ETU1
AUX0–AUX1
EIA, EIB, EIZ,
EIS
12
2
2
I/O
I
O
4
I
Encoder Interface Inputs and
External Registration Inputs
No Connect
Analog Power Supply
Analog Ground
Digital Power Supply
Digital Ground
NC
AVDD
AVSS
VDD
GND
2
2
2
8
16
SUP
GND
SUP
GND
INTERRUPT OVERVIEW
The ADMC401 can respond to different interrupt sources, some
of which are internal DSP core interrupts and others from the
motor control peripherals. The DSP core interrupts include a:
Power up (or
RESET
) interrupt.
A peripheral (or
IRQ2)
interrupt.
A SPORT0 receive and a SPORT0 transmit interrupt.
A SPORT1 receive (or
IRQ0
) and a SPORT1 transmit (or
IRQ1
) interrupt.
Two software interrupts.
An interval timer timeout interrupt.
A power-down interrupt.
In addition, the motor control peripherals add other interrupts
that include:
A PWMSYNC interrupt.
An ADC end of conversion interrupt.
An encoder loop timer timeout interrupt.
Five peripheral input/output (PIO) interrupts.
An event timer interrupt.
An encoder count error interrupt.
A PWM trip interrupt.
The interrupts are internally prioritized and individually maskable
except for the nonmaskable power-down interrupt.
Memory Map
The ADMC401 has two distinct memory types; program memory
and data memory (in addition to external boot memory). In
general, program memory contains user code and coefficients,
while the data memory is used to store variables and data during
program execution. Both program memory RAM and ROM is
provided internally on the ADMC401. The program memory
map of the ADMC401 can be altered depending on the state of
the MMAP and BMODE pins. The various program memory
maps are illustrated in Figure 11 for the permissible settings of
MMAP and BMODE. The state of these pins also impact the
way in which the internal memory of the ADMC401 is booted,
as described later.
There is 2K of internal ROM on the ADMC401. Setting the
ROMENABLE bit on the Data Memory Wait State Control
Register (at address DM (0x3FFE)) enables the ROM. When the
ROMENABLE bit is set to 1, addressing program memory in the
ROM range will access the on-chip ROM. When ROMENABLE
is set to zero, addressing program memory in this range will
access external program memory. The ROMENABLE bit is
initialized to zero after reset unless MMAP and BMODE = 1.
When MMAP = BMODE = 0, the ADMC401 provides 2K
×
24
bits of internal program memory RAM starting at address
0x0000 that is booted from a byte-wide interface on the address
and data buses. Following boot loading, program execution
starts at address 0x0000. In this mode, the remainder of the
program memory space, a 12K
×
24-bit block starting at address
0x1000, is assigned to external memory.
When MMAP = BMODE = 1, the program memory map is
identical to the previous case, but ROMENABLE defaults to 1 at
reset, and execution starts from the internal program memory
ROM located at address 0x0800. This permits the internal (and
external if desired) memory to be boot loaded across the various
serial interfaces on SPORT1.
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