參數(shù)資料
型號： ADMC401
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： Single-Chip, DSP-Based High Performance Motor Controller
中文描述： 24-BIT, 13 MHz, OTHER DSP, PQFP144
封裝： TQFP-144
文件頁數(shù)： 29/60頁
文件大小： 417K
代理商： ADMC401
ADMC401
–29–
REV. B
For example, for a 26 MHz CLKOUT and a desired PWM
switching frequency of 10 kHz (T
S
= 100
μ
s), the correct value
to load into the PWMTM register is:
PWMTM
=
=
26 10
2 10 10
1300
6
3
The largest value that can be written to the 16-bit PWMTM
register is 0xFFFF = 65,535, which corresponds to a minimum
PWM switching frequency of:
f
Hz
PWM MIN
,
,
=
=
26 10
2 65 535
198
6
PWM Switching Dead Time, PWMDT Register
The second important parameter that must be set up in the
initial configuration of the PWM block is the switching dead
time. This is a short delay time introduced between turning off
one PWM signal (say AH) and turning on the complementary
signal, AL. This short time delay is introduced to permit the
power switch being turned off (AH in this case) to completely
recover its blocking capability before the complementary switch
is turned on. This time delay prevents a potentially destructive
short-circuit condition from developing across the dc link capacitor
of a typical voltage source inverter.
The dead time is controlled by the 10-bit PWMDT register.
There is one dead time register that controls the dead time
inserted into the three pairs of PWM output signals. The dead
time, T
D
, is related to the value in the PWMDT register by:
T
PWMDT
t
D
CK
=
× ×
2
Therefore, for a 26 MHz CLKOUT, a
PWMDT
value of
0x00A (= 10) introduces a 770 ns delay between the turn-off
on any PWM signal (say AH) and the turn-on of its complemen-
tary signal (AL). The amount of the dead time can therefore be
programmed in increments of 2t
CK
(or 77 ns for a 26 MHz
CLKOUT). The PWMDT register is a 10-bit register so that its
maximum value is 0x3FF (= 1023) corresponding to a maximum
programmed dead time of:
T
t
s
D MAX
,
CK
–
.
.
=
×
×
=
×
×
×
=
1023
2
1023
2
38 5
10
78 8
9
μ
for a CLKOUT rate of 26 MHz. Obviously, the dead time can
be programmed to be zero by writing 0 to the PWMDT register.
PWM Operating Mode, MODECTRL and SYSSTAT Registers
The PWM controller of the ADMC401 can operate in two
distinct modes; single update mode and double update mode.
The operating mode of the PWM controller is determined by
the state of Bit 6 of the MODECTRL register. If this bit is
cleared, the PWM operates in the single update mode. Setting
Bit 6 places the PWM in the double update mode. By default,
following reset, Bit 6 of the MODECTRL register is cleared so
that the default operating mode is in single update mode.
In single update mode, a single PWMSYNC pulse is produced
in each PWM period. The rising edge of this signal marks the
start of a new PWM cycle and is used to latch new values from
the PWM configuration registers (PWMTM, PWMDT, PWMPD
and PWMSYNCWT) and the PWM duty cycle registers
(PWMCHA, PWMCHB and PWMCHC) into the three-phase
timing unit. In addition, the PWMSEG register is also latched
into the output control unit on the rising edge of the PWMSYNC
pulse. In effect, this means that the characteristics and resultant
duty cycles of the PWM signals can be updated only once per
PWM period at the start of each cycle. The result is that PWM
patterns that are symmetrical about the midpoint of the switch-
ing period are produced.
In double update mode, an additional PWMSYNC pulse is
produced at the midpoint of each PWM period. The rising edge
of this new PWMSYNC pulse is again used to latch new values
of the PWM configuration registers, duty cycle registers and the
PWMSEG register. As a result it is possible to alter the charac-
teristics (switching frequency, dead time, minimum pulsewidth
and PWMSYNC pulsewidth) as well as the output duty cycles
at the midpoint of each PWM cycle. Consequently, it is possible
with double update mode to produce PWM switching patterns
that are not symmetrical about the midpoint of the period (asym-
metrical PWM patterns).
In the double update mode, it may be necessary to know whether
operation at any point in time is in either the first half or the
second half of the PWM cycle. This information is provided by
Bit 3 of the SYSSTAT register, which is cleared during opera-
tion in the first half of each PWM period (between the rising
edge of the original PWMSYNC pulse and the rising edge of the
new PWMSYNC pulse introduced in double update mode). Bit
3 of the SYSSTAT register is set during operation in the second
half of each PWM period. This status bit allows the user to make a
determination of the particular half-cycle during implementation
of the PWMSYNC interrupt service routine, if required.
The advantage of the double update mode is that lower harmonic
voltages can be produced by the PWM process and faster
control bandwidths are possible. However, for a given PWM
switching frequency, the PWMSYNC pulses occur at twice the
rate in the double update mode. Since new duty cycle values
must be computed in each PWMSYNC interrupt service routine,
there is a larger computational burden on the DSP in the double
update mode. Alternatively, the same PWM update rate may be
maintained at half the switching frequency to give lower switch-
ing losses.
Width of the PWMSYNC Pulse, PWMSYNCWT Register
The PWM controller of the ADMC401 produces an output
PWM synchronization pulse at a rate equal to the PWM switch-
ing frequency in single update mode and at twice the PWM
frequency in the double update mode. This pulse is available
for external use at the PWMSYNC pin. The width of this
PWMSYNC pulse is programmable by the 8-bit read/write
PWMSYNCWT register. The width of the PWMSYNC pulse,
T
PWMSYNC
, is given by:
(
so that the width of the pulse is programmable from t
CK
to 256
×
t
CK
(corresponding to 38.5 ns to 9.85
μ
s for a CLKOUT rate of
26 MHz). Following a reset, the PWMSYNCWT register con-
tains 0x27 (= 39) so that the default PWMSYNC width is
1.54
μ
s, again for a 26 MHz CLKOUT.
PWM Duty Cycles, PWMCHA, PWMCHB, PWMCHC
Registers
The duty cycles of the six PWM output signals on Pins AH to
CL are controlled by the three 16-bit read/write duty cycle
registers, PWMCHA, PWMCHB and PWMCHC. The integer
value in the register PWMCHA controls the duty cycle of the
signals on AH and AL, in PWMCHB controls the duty cycle of
the signals on BH and BL and in PWMCHC controls the duty
T
t
PWMSYNCWT
PWMSYNC
CK
=
×
+
)
1
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