參數(shù)資料
型號(hào)： ADMC401
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： Single-Chip, DSP-Based High Performance Motor Controller
中文描述： 24-BIT, 13 MHz, OTHER DSP, PQFP144
封裝： TQFP-144
文件頁(yè)數(shù)： 5/60頁(yè)
文件大小： 417K
代理商： ADMC401
ADMC401
–5–
REV. B
Parameter
Clock Signals
t
CK
is defined as 0.5t
CKI.
The ADMC401 uses an input clock
with a frequency equal to half the instruction rate; a 13 MHz
clock (which is equivalent to 76.9 ns) yields a 38.5 ns processor
cycle (equivalent to 26 MHz). t
CK
values within the range of
0.5t
period should be substituted for all relevant timing
parameters to obtain specification value.
Example: t
CKH
= 0.5t
CK
– 10 ns = 0.5 (38.5 ns) – 10 ns = 9.25 ns.
Timing Requirements:
t
CKI
CLKIN Period
t
CKIL
CLKIN Width Low
t
CKIH
CLKIN Width High
Switching Characteristics:
t
CKL
CLKOUT Width Low
t
CKH
CLKOUT Width High
t
CKOH
CLKIN High to CLKOUT High
Control Signals
Timing Requirement:
t
RSP
RESET
Width Low
PWM Shutdown Signals
Timing Requirements:
t
PWMTPW
PWMTRIP
Width Low
t
PIOPWM
PIO Width Low
ADC Signals
T
iming Requirements:
t
CSI
Internal Convert Start Width High
t
CSE
External Convert Start Width High
Min
Max
Unit
76.9
20
20
150
ns
ns
ns
0.5t
CK
– 10
0.5t
CK
– 10
0
ns
ns
ns
20
5t
CK
1
ns
t
CK
2t
CK
ns
ns
2t
CK
2t
CK
ns
ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
CLKIN
CLKOUT
t
CKOH
t
CKI
t
CKIH
t
CKIL
t
CKH
t
CKL
Figure 1. Clock Signals
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