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參數(shù)資料
| 型號(hào)： | ADMC401-PB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Single-Chip, DSP-Based High Performance Motor Controller |
| 中文描述： | 單芯片，基于DSP的高性能電機(jī)控制器 |
| 文件頁數(shù)： | 56/60頁 |
| 文件大小： | 417K |
| 代理商： | ADMC401-PB |
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REV. B
ADMC401
–56–
DM (0x3FFC)
TPERIOD (R/W)
TCOUNT (R/W)
TSCALE (R/W)
9
8
DM (0x3FFD)
DM (0x3FFB)
15
14
13
12
11
10
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
SSTAT (R)
PC STACK EMPTY
PC STACK OVERFLOW
COUNT STACK EMPTY
COUNT STACK OVERFLOW
STATUS STACK EMPTY
STATUS STACK OVERFLOW
LOOP STACK EMPTY
LOOP STACK OVERFLOW
7
6
5
4
3
2
1
0
1
0
1
0
1
0
1
0
MSTAT (R/W)
4
3
6
5
2
1
0
0
0
0
0
0
0
0
DSP REGISTER
DATA REGISTER BANK SELECT
0 = PRIMARY, 1 = SECONDARY
BIT REVERSE MODE ENABLE (DAG1)
ALU OVERFLOW LATCH MODE ENABLE
AR SATURATION MODE ENABLE
MAC RESU PLACEMENT
0 = FRACTIONAL,LT 1 = INTERGER
TIMER ENABLE
GO MODE ENABLE
SYSCNTL (R/W)
PWAIT
PROGRAM MEMORY
WAIT STATES
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BPAGE
BOOT PAGE SELECT
BWAIT
BOOT WAIT STATES
BFORCE
BOOT FORCE BIT
SPORT0 ENABLE
1 = ENABLE, 0 = DISABLED
1
0
1
0
0
0
0
0
1
1
1
1
1
0
0
0
DM (0x3FFF)
SPORT1 ENABLE
1 = ENABLE, 0 = DISABLED
SPORT1 CONFIGURE
1 = SERIAL PORT
0 = FI, FO, IRQ0, IRQ1, SCLK
AZ ALU RESULT ZERO
AN ALU RESULT NEGATIVE
AV ALU OVERFLOW
AC ALU CARRY
AS ALU X INPUT SIGN
AQ ALU QUOTIENT
MV MAC OVERFLOW
SS SHIFTER INPUT SIGN
7
6
5
4
3
2
1
0
ASTAT (R/W)
0
0
0
0
0
0
0
0
DSP REGISTER
DSP REGISTER
Figure 44 Structure of Registers of ADMC401
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
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