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參數(shù)資料
| 型號： | ADMC401-PB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Single-Chip, DSP-Based High Performance Motor Controller |
| 中文描述： | 單芯片，基于DSP的高性能電機(jī)控制器 |
| 文件頁數(shù)： | 39/60頁 |
| 文件大?。?/td> | 417K |
| 代理商： | ADMC401-PB |
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ADMC401
–39–
REV. B
EIU/EET Registers
The structure and functionality of the EIU and EET registers
are illustrated at the end of the data sheet. The characteristics of
the EIU block at 26 MHz are given in Table VI.
PROGRAMMABLE DIGITAL INPUT/OUTPUT
OVERVIEW
The ADMC401 has 12 programmable digital input/output pins
called PIO0 to PIO11. Each pin may be individually configured
as either an input or an output. An associated data register may
be used to read data from pins configured as inputs and write
data to pins configured as outputs. In addition, each I/O line
may be configured as an interrupt source. Both edge (rising and
falling) and level (high and low) interrupts may be detected.
Four of the PIO lines (PIO0 to PIO3) have dedicated vector
addresses in the interrupt table. The remaining eight interrupts
(PIO4 to PIO11) are multiplexed into a single additional inter-
rupt vector location. The PIOFLAG register is used to deter-
mine which line caused the interrupt. In addition, all PIO lines
may be alternatively configured as PWM trip sources. The
PIOPWM register has dedicated bits that may be used to enable
this function on each PIO line. In this mode, a low level on any
pins configured as a PWM trip source shuts down the PWM in
a manner identical to the
PWMTRIP
pin.
PIO CONFIGURATION
Each of the 12 programmable input/output lines may be config-
ured as either an input or an output by programming the appro-
priate bits of the PIODIR register. This 12-bit register has one
bit associated with each I/O line; Bit 0 corresponds to PIO0, etc.
Clearing a bit in the PIODIR register will configure the corre-
sponding pin as an input line. Conversely, setting a bit config-
ures the pin as an output pin. On reset, all bits of the PIODIR
register are cleared so that all 12 PIO pins are configured as inputs.
In addition, all PIO lines have internal pull-down resistors in the
ADMC401 so that unconnected lines are seen as low level inputs.
PIO DATA READING/WRITING
Associated with the PIO system is a data register, PIODATA,
that also has a bit associated with each I/O line. Data written to
the PIODATA register will appear on those pins configured as
outputs. Reading the PIODATA register will read the data from
those pins configured as inputs.
PIO INTERRUPT GENERATION
Each of the 12 PIO lines may be configured as an interrupt
source. Four of the PIO lines, PIO0 to PIO3, have dedicated
interrupt vector locations, whereas the remaining eight are mul-
tiplexed into an additional interrupt vector. The PIOINTEN
register is used to enable or disable the interrupt mode on the
PIO4 to PIO11 lines. The PICMASK register of the program-
mable interrupt controller is used to enable interrupts on the
four dedicated PIO lines, PIO0 to PIO3, and to enable the
usage of PIOINTEN for interrupts on the other PIOs.
Interrupts may be generated on either edge (rising or falling) or
level (high or low) events by programming the appropriate bits
of both the PIOMODE and PIOLEVEL registers. Both registers
have a dedicated bit for each of the twelve PIO lines. Setting the
appropriate bit of the PIOMODE register configures the inter-
rupt as level sensitive whereas clearing the bit configures the
interrupt for edge sensitive. In level-sensitive mode (PIOMODE
bit is 1), setting the corresponding bit in the PIOLEVEL regis-
ter configures the interrupt as active high, whereas clearing the
bit configures it for active low. In edge-sensitive mode (PIOMODE
bit is 0), setting the corresponding bit of the PIOLEVEL register
configures the interrupt for rising edge, whereas clearing the bit
configures the interrupt for falling edge. On reset, all PIO inter-
rupts are disabled.
The four dedicated PIO interrupts from PIO0 to PIO3 have
interrupt vector addresses at program memory addresses 0x0048
for PIO0, 0x004C for PIO1, 0x0050 for PIO2 and 0x0054 for
PIO3. In the event of an interrupt on PIO4 to PIO11, the corre-
sponding bit of the PIOFLAG register is set and the general
PIO interrupt is activated. This interrupt has a dedicated vector
address at location 0x003C. In the interrupt service routine for
this interrupt, the user must poll the PIOFLAG register to de-
termine which of the PIO4 to PIO11 lines, that have interrupts
enabled, caused the interrupt. Of course, if only one of the PIO4 to
PIO11 lines has interrupts enabled, no polling is necessary.
PIO lines that are configured as outputs may also be used to
generate interrupts. If, for example, one of the PIO lines is con-
figured simultaneously as an output and as an interrupt source,
writing the appropriate data sequence to that line will trigger an
interrupt.
PIO AS
PWMTRIP
SOURCES
By setting the appropriate bits of the PIOPWM register, each of
the twelve PIO lines can be configured as a PWM shutdown
source. In this mode, a low level on the PIO pin will cause a
PWM shutdown command that will disable all six PWM out-
puts on AH to CL. Since the disabling of the PWM is indepen-
dent of the DSP clock, so that the PWM stage can be fully
protected even in the event of a loss of clock signal to the DSP.
In addition, a PWMTRIP interrupt will be generated when the
PWM is shutdown. However, it is also possible to generate the
normal PIO interrupts on the occurrence of a falling-edge on
the PIO line. The advantage of this highly flexible structure for
PWM shutdown is that multiple fault signals could be applied to
the ADMC401 at different PIO lines. The occurrence of a falling-
Table VI. Fundamental Characteristics of Encoder Interface Unit of ADMC401 (At 26 MHz)
Parameter
Test Conditions
Min
Typ
Max
Unit
f
ENC
f
QUAD
Encoder Input (EIA, EIB) Rate
Quadrature Rate
Encoder Loop Timer Timeout Rate
4.33
17.3
MHz
MHz
ns
sec
ns
μ
s
38.5
0.645
T
MINENC
Minimum Encoder Pulsewidth
EIUFILTER = 0x00
EIUFILTER = 0x3F
116
7.39
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