參數(shù)資料
型號(hào)： ADMC401-PB
廠商： Analog Devices, Inc.
英文描述： Single-Chip, DSP-Based High Performance Motor Controller
中文描述： 單芯片，基于DSP的高性能電機(jī)控制器
文件頁(yè)數(shù)： 53/60頁(yè)
文件大?。?/td> 417K
代理商： ADMC401-PB
ADMC401
–53–
REV. B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
DM (0x2011)
ADC END OF CONVERSION
PWMSYNC
EIU LOOP TIMER TIMEOUT
PIO4 - PIO11 INTERRUPT
EIU COUNT ERROR INTERRUPT
DM (0x201D)
PICMASK (R/W)
8
7
15
14
13
12
11
10
9
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
DM (0x2012)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DM (0x2013)
0 = DISABLE INTERRUPT (MASK)
1 = ENABLE INTERRUPT
PWM TRIP INTERRUPT
PIO3 INTERRUPT
PIO2 INTERRUPT
PIO1 INTERRUPT
PIO0 INTERRUPT
ETU INTERRUPT
1
1
1
1
1
1
1
1
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
AUXCH0 (R/W)
DM (0x2010)
1
1
1
1
1
1
1
1
TON, AUX0 = 2 AUXCH0 tCK
AUXTM0 (R/W)
AUXTM1 (R/W)
TAUX1 = 2 AUXCH1 tCK
TON, AUX0 = 2 (AUXTM0+1) tCK
TAUX1 = 2 (AUXTM1+1) tCK IN INDEPENDENT MODE
TOFFSET = 2 (AUXTM1+1) tCK IN OFFSET MODE
AUXCH1 (R/W)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 41. Structure of Registers of ADMC401
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—
these bits should always be written as shown.
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