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參數(shù)資料
| 型號(hào)： | ADM9240 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Cost Microprocessor System Hardware Monitor |
| 中文描述： | 低成本的微處理器系統(tǒng)硬件監(jiān)視器 |
| 文件頁數(shù)： | 5/22頁 |
| 文件大小： | 280K |
| 代理商： | ADM9240 |
ADM9240
–5–
REV. 0
PIN FUNCT ION DE SCRIPT IONS
Pin Number
Mnemonic
Description
1
NT EST _OUT /A0
Digital I/O. Dual Function Pin. T he lowest order programmable bit of the Serial Bus Address.
T his pin functions as an output when doing a NAND T ree test.
Digital Input. T he highest order programmable bit of the Serial Bus Address.
Digital I/O. Serial Bus Bidirectional Data. Open-drain output.
Digital Input. Serial Bus Clock.
Digital Input. 0 to V
CC
amplitude fan tachometer input.
Digital Input. 0 to V
CC
amplitude fan tachometer input.
Digital I/O. An active high input from an external circuit that latches a Chassis Intrusion
event. T his line can go high without any clamping action regardless of the powered state of
the ADM9240. T he ADM9240 provides an internal open drain on this line, controlled by
Bit 6 of Register 40h or Bit 7 of Register 46h, to provide a minimum 20 ms pulse on this line,
to reset the external Chassis Intrusion Latch.
Digital Ground. Internally connected to all of the digital circuitry.
Power (+2.85 V to +5.75 V). T ypically powered from +3.3 V or +5 V power rail. Bypass with
the parallel combination of 10
μ
F (electrolytic or tantalum) and 0.1
μ
F (ceramic) bypass
capacitors.
Digital Output. Interrupt Request (open drain). T he output is enabled when Bit 1 of the
Configuration Register is set to 1. T he default state is disabled.
Digital Input/Analog Output. An active-high input that enables NAND T ree mode board-
level connectivity testing. Refer to section on NAND T ree testing. Also functions as a pro-
grammable analog output when NAND T ree is not selected
Digital I/O. Master Reset, 5 mA driver (open drain), active low output with a 20 ms minimum
pulsewidth. Available when enabled via Bit 7 in Register 44h, and set using Bit 4 in Register
40h. Also acts as reset input when pulled low (e.g., power-on reset).
Analog Ground. Internally connected to all analog circuitry. T he ground reference for all
analog inputs.
Analog Input. Monitors processor core voltage +V
CCP2
(0 V–3.6 V). Can also be used to
monitor the –12 V supply by adding two external resistors.
Analog Input. Monitors +12 V supply.
Analog Input. Monitors +5 V supply.
Analog Input. Monitors +3.3 V supply.
Analog Input. Monitors +2.5 V supply.
Analog Input. Monitors processor core voltage +V
CCP1
(0 V–3.6 V).
Digital Input. Core Voltage ID readouts from the processor. T his value is read into the
VID4 Status Register.
Digital Input. Core Voltage ID readouts from the processor. T his value is read into the
VID0–VID3 Status Register.
Digital Input. Core Voltage ID readouts from the processor. T his value is read into the
VID0–VID3 Status Register.
Digital Input. Core Voltage ID readouts from the processor. T his value is read into the
VID0–VID3 Status Register.
Digital Input. Core Voltage ID readouts from the processor. T his value is read into the
VID0–VID3 Status Register.
2
3
4
5
6
7
A1
SDA
SCL
FAN1
FAN2
CI
8
9
GNDD
V
CC
10
INT
11
NT EST _IN/AOUT
12
RESET
13
GNDA
14
+V
CCP2
15
16
17
18
19
20
+12 V
IN
+5 V
IN
+3.3 V
IN
+2.5 V
IN
+V
CCP1
VID4
21
VID3
22
VID2
23
VID1
24
VID0
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相關(guān)代理商/技術(shù)參數(shù) |
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| ADM9240ARU-REEL7 | 制造商:Analog Devices 功能描述: |
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