參數(shù)資料
型號(hào)： ADM9240
廠商： Analog Devices, Inc.
英文描述： Low Cost Microprocessor System Hardware Monitor
中文描述： 低成本的微處理器系統(tǒng)硬件監(jiān)視器
文件頁(yè)數(shù)： 14/22頁(yè)
文件大?。?/td> 280K
代理商： ADM9240
ADM9240
–14–
REV. 0
T he chassis intrusion circuit should be designed so that it can be
reset by pulling its output low. A suitable chassis intrusion cir-
cuit using a phototransistor is shown in Figure 8. Light falling
on the phototransistor when the PC cover is removed will cause
it to turn on and pull up the input of N1, thus setting the latch
N3/N4. After the cover is replaced, a low reset on the CI output
will pull down the input of N4, resetting the latch.
+5V
CMOS
BACKUP
BATTERY
1N914
1N914
CI
74HC132
470k
V
MRD901
100k
V
10k
V
Figure 8a. Chassis Intrusion Detector and Latch
T he Chassis Intrusion input can also be used for other types of
alarm input. Figure 8b shows a temperature alarm circuit using
an AD22105 temperature switch sensor. T his produces a low-
going output when the preset temperature is exceeded, so the
output is inverted by Q1 to make it compatible with the CI
input. Q1 can be almost any small-signal NPN transistor, or a
T T L or CMOS inverter gate may be used if one is available. See
the AD22105 data sheet for information on selecting R
SET
.
CONFIGURATION
REGISTER
INT
_ENABLE
INT
_CLEAR
INT
CI (CHASSIS INTRUSION)
DATA
DEMULTIPLEXER
HIGH AND
LOW LIMIT
COMPARATORS
+V
CCP2
+12V
+5V
+3.3V
+2.5V
+V
CCP1
FAN1
FAN2
TEMP
HIGH LIMIT
LOW LIMIT
VALUE
FROM VALUE
AND LIMIT
REGISTERS
1 = OUT
OF LIMIT
MASKING DATA
FROM BUS
INTERRUPT
STATUS
REGISTERS
STATUS
BIT
MASK
BIT
MASK GATING
3
10
INTERRUPT
MASK
REGISTERS
Figure 9. Interrupt Register Structure
R1
10k
V
V
C
CI
AD22105
TEMP.
SENSOR
R
SET
Q1
Figure 8b. Using the CI Input with a Temperature Sensor
Note: T he chassis intrusion input does not have a protective
clamp diode to V
CC
, as this could pull down the chassis intru-
sion latch and reset it when the ADM9240 was powered down.
T HE ADM9240 INT E RRUPT ST RUCT URE
T he Interrupt Structure of the ADM9240 is shown in Figure 9.
As each measurement value is obtained and stored in the
appropriate value register, the value and the limits from the
corresponding limit registers are fed to the high and low limit
comparators. T he result of each comparison (1 = out of limit,
0 = in limit) is routed to the corresponding bit input of the
Interrupt Status Registers via a data demultiplexer and used to
set that bit high or low as appropriate.
T he Interrupt Mask Registers have bits corresponding to each of
the Interrupt Status Register Bits. Setting an Interrupt Mask Bit
high forces the corresponding Status Bit output low, while set-
ting an Interrupt Mask Bit low allows the corresponding Status
Bit to be asserted. After masking, the status bits are all ORed
together to produce the
INT
output, which will pull low if any
unmasked status bit goes high, i.e., when any measured value
goes out of limit.
T he
INT
output is enabled when Bit 1 of the Configuration
Register (
INT
_Enable) is high, and Bit 3 (
INT
_Clear) is low.
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