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參數(shù)資料
| 型號： | ADF4002BRUZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/20頁 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQUENCY SYNTH 16-TSSOP |
| 設計資源： | Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003) |
| 標準包裝： | 1,000 |
| 類型： | 時鐘/頻率合成器（RF），相位檢測器 |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4002EBZ1-ND - BOARD EVAL FOR ADF4002 |
ADF4002
Data Sheet
Rev. C | Page 8 of 20
THEORY OF OPERATION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 10. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
100k
NC
REFIN
NC
NO
SW1
SW2
BUFFER
SW3
TO R COUNTER
POWER-DOWN
CONTROL
06052-
013
Figure 10. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 11. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the N counter.
500
1.6V
500
AGND
BIAS
GENERATOR
RFINA
RFINB
AVDD
06052-
014
Figure 11. RF Input Stage
N COUNTER
The N CMOS counter allows a wide ranging division ratio in
the PLL feedback counter. Division ratios from 1 to 8191 are
allowed.
N and R Relationship
The N counter makes it possible to generate output frequencies
that are spaced only by the reference frequency divided by R.
The equation for the VCO frequency is
R
f
N
f
REFIN
VCO
×
=
where:
fVCO is the output frequency of external voltage controlled
oscillator (VCO).
N is the preset divide ratio of binary 13-bit counter (1 to 8191).
fREFIN is the external reference frequency oscillator.
TO PFD
FROM RF
INPUT STAGE
FROM N
COUNTER LATCH
13-BIT N
COUNTER
06052-
021
Figure 12. N Counter
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 13 is a simplified schematic.
The PFD includes a programmable delay element that controls
the width of the antibacklash pulse. This pulse ensures that
there is no dead zone in the PFD transfer function, and
minimizes phase noise and reference spurs. Two bits in the
reference counter latch (ABP2 and ABP1) control the width of
the pulse. See Figure 16 for details. The smallest antibacklash
pulse width is not recommended.
HI
D1
D2
Q1
Q2
CLR1
CLR2
CP
U1
U2
UP
DOWN
ABP2
ABP1
CPGND
U3
R DIVIDER
PROGRAMMABLE
DELAY
N DIVIDER
VP
CHARGE
PUMP
06052-
023
Figure 13. PFD Simplified Schematic and Timing (In Lock)
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