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參數(shù)資料
| 型號(hào)： | ADF4007BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 1/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DIVIDER/PLL SYNTHESZR 20LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 時(shí)鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無(wú) |
| 頻率 - 最大： | 7.5GHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4007EBZ1-ND - BOARD EVALUATION FOR ADF4007EB1 |
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High Frequency Divider/PLL Synthesizer
Data Sheet
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2004–2012 Analog Devices, Inc. All rights reserved.
FEATURES
7.5 GHz bandwidth
Maximum PFD frequency of 120 MHz
Divide ratios of 8, 16, 32, or 64
2.7 V to 3.3 V power supply
Separate charge pump supply (V
P) allows extended tuning
voltage in 3 V systems
R
SET control of charge pump current
Hardware power-down mode
APPLICATIONS
Satellite communications
Broadband wireless access
CATV
Instrumentation
Wireless LANs
GENERAL DESCRIPTION
The ADF4007 is a high frequency divider/PLL synthesizer that
can be used in a variety of communications applications. It can
operate to 7.5 GHz on the RF side and to 120 MHz at the PFD.
It consists of a low noise digital PFD (phase frequency detector), a
precision charge pump, and a divider/prescaler. The divider/
prescaler value can be set by two external control pins to one of
four values (8, 16, 32, or 64). The reference divider is permanently
set to 2, allowing an external REFIN frequency of up to 240 MHz.
A complete PLL (phase-locked loop) can be implemented if the
synthesizer is used with an external loop filter and a VCO (voltage
controlled oscillator). Its very high bandwidth means that
frequency doublers can be eliminated in many high frequency
systems, simplifying system architecture and reducing cost.
FUNCTIONAL BLOCK DIAGRAM
REFIN
RFINA
RFINB
VDD
N2
N1
GND
R COUNTER
÷ 2
MUX
MUXOUT
CPGND
RSET
VP
CP
PHASE
FREQUENCY
DETECTOR
REFERENCE
CHARGE
PUMP
ADF4007
N COUNTER
÷ 8, ÷ 16,
÷ 32, ÷ 64
M2
M1
04537-
001
Figure 1.
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