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參數(shù)資料
| 型號： | ADF4002BRUZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/20頁 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQUENCY SYNTH 16-TSSOP |
| 設計資源： | Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003) |
| 標準包裝： | 1,000 |
| 類型： | 時鐘/頻率合成器（RF），相位檢測器 |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4002EBZ1-ND - BOARD EVAL FOR ADF4002 |
ADF4002
Data Sheet
Rev. C | Page 18 of 20
ADuC812 Interface
Figure 22 shows the interface between the ADF4002 and the
ADuC812 MicroConverter. Because the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4002 needs a
24-bit word. This is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. When the third byte
has been written, bring the LE input high to complete the
transfer.
On first applying power to the ADF4002, it needs four writes
(one each to the initialization latch, function latch, R counter
latch, and N counter latch) for the output to become active.
I/O port lines on the ADuC812 are also used to control power-
down (CE input) and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
When operating in the SPI master mode, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed is 166 kHz.
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
MOSI
SCLOCK
I/O PORTS
ADuC812
ADF4002
06052-
019
Figure 22. ADuC812 to ADF4002 Interface
ADSP21xx Interface
Figure 23 shows the interface between the ADF4002 and the
ADSP21xx digital signal processor. The ADF4002 needs a
24-bit serial word for each latch write. The easiest way to accom-
plish this using the ADSP21xx family is to use the autobuffered
transmit mode of operation with alternate framing. This provides
a means for transmitting an entire block of serial data before an
interrupt is generated. Set up the word length for eight bits and
use three memory locations for each 24-bit word. To program
each 24-bit latch, store the three 8-bit bytes, enable the
autobuffered mode, and then write to the transmit register of
the DSP. This last operation initiates the autobuffer transfer.
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
ADSP21xx
ADF4002
DT
SCLK
I/O FLAGS
TFS
06052-
020
Figure 23. ADSP21xx to ADF4002 Interface
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the lead frame chip scale package (CP-20-1) are
rectangular. The printed circuit board pad for these should be
0.1 mm longer than the package land length and 0.05 mm wider
than the package land width. The land should be centered on
the pad. This ensures that the solder joint size is maximized.
The bottom of the lead frame chip scale package has a central
thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern. This ensures that
shorting is avoided.
Thermal vias can be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated into the thermal pad at a
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm and the via barrel should be plated with 1 oz
copper to plug the via.
The user should connect the printed circuit board thermal pad
to AGND.
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| ADF4002SRUZ-EP | 功能描述:IC PLL FREQUENCY SYNTH 16TSSOP 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標準包裝:96 |
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