參數(shù)資料
型號： ADAU1702JSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 9/52頁
文件大?。?/td> 0K
描述： IC AUDIO PROC 2ADC/4DAC 48-LQFP
標準包裝： 1
系列： SigmaDSP®
類型： 音頻處理器
應用： 車載，監(jiān)視器，MP3
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
產(chǎn)品目錄頁面： 776 (CN2011-ZH PDF)
ADAU1702
Rev. C | Page 17 of 52
INITIALIZATION
This section details the procedure for properly setting up the
ADAU1702. The following five-step sequence provides an
overview of how to initialize the IC:
1.
Apply power to ADAU1702.
2.
Wait for PLL to lock.
3.
Load the SigmaDSP program and parameters.
4.
Set up the registers (including multipurpose pins and
digital interfaces).
5.
Turn off the default muting of the converters, clear the
data registers, and initialize the DAC setup register (see
the Control Registers Setup section for specific settings).
POWER-UP SEQUENCE
The ADAU1702 has a built-in power-up sequence that
initializes the contents of all internal RAMs on power-up or
when the device is brought out of a reset. On the positive edge
of RESET, the contents of the Internal Program Boot ROM are
copied to the Internal Program RAM memory, the parameter,
RAM, is filled with values (all 0s) from its associated Boot
ROM, and all registers are initialized to 0s. The default Boot
ROM program copies audio from the inputs to the outputs
without processing it (see
). In this program, serial
digital Input 0 and Input 1 are output on DAC0 and DAC1 and
serial digital Output 0 and Output 1. ADC0 and ADC1 are
output on DAC2 and DAC3. The data memories are also zeroed
at power-up. Do not write new values to the control port until
the initialization is complete.
Table 10. Power-Up Time
MCLKI Input
Init.
Time
Max Program/
Parameter/Register
Boot Time (I2C)
Total
3.072 MHz (64 × fS)
85 ms
133 ms
218 ms
11.289 MHz (256 × fS)
23 ms
133 ms
156 ms
12.288 MHz (256 × fS)
21 ms
133 ms
154 ms
18.432 MHz (384 × fS)
16 ms
133 ms
149 ms
24.576 MHz (512 × fS)
11 ms
133 ms
144 ms
The PLL start-up time lasts for 218 cycles of the clock on the
MCLKI pin. This time ranges from 10.7 ms for a 24.576 MHz
(512 × fS) input clock to 85.3 ms for a 3.072 MHz (64 × fS) input
clock and is measured from the rising edge of RESET. Following
the PLL startup, the duration of the ADAU1702 boot cycle is about
42 μs for a fS of 48 kHz. The user should avoid writing to or reading
from the ADAU1702 during this start-up time.
For an MCLK input of 12.288 MHz, the full initialization
sequence (PLL startup plus boot cycle) is approximately 21 ms.
As the device comes out of a reset, the clock mode is
immediately set by the PLL_MODE0 and PLL_MODE1 pins.
The reset is synchronized to the falling edge of the internal clock.
Table 10 lists typical times to boot the ADAU1702 into an
operational state of an application, assuming a 400 kHz I2C
clock loading a full program, parameter set, and all registers
(about 6.5 kB). In reality, most applications do not fill the RAMs
and therefore boot time (Column 3 of Table 10) is less.
CONTROL REGISTERS SETUP
The following registers must be set as described in this section
to initialize the ADAU1702. These settings are the basic minimum
settings needed to operate the IC with an analog input/output of
48 kHz. More registers may need to be set, depending on the
application. See the RAMs and Registers section for additional
settings.
DSP Core Control Register (Address 2076)
Set Bits[4:2] (ADM, DAM, and CR) each to 1.
DAC Setup Register (Address 2087)
Set Bits[0:1] (DS[1:0]) to 01.
RECOMMENDED PROGRAM/PARAMETER
LOADING PROCEDURE
When writing large amounts of data to the program or para-
meter RAM in direct write mode, the processor core should
be disabled to prevent unpleasant noises from appearing in
the audio output.
1.
Set Bit 3 and Bit 4 (active low) of the core control register
to 1 to mute the ADCs and DACs. This begins a volume
ramp-down.
2.
Set Bit 2 (active low) of the core control register to 1. This
zeroes the SigmaDSP accumulators, the data output registers,
and the data input registers.
3.
Fill the program RAM using burst mode writes.
4.
Fill the parameter RAM using burst mode writes.
5.
Deassert Bit 2 to Bit 4 of the core control register.
ADC0
DAC1
DAC0
DAC2
DAC3
ADC1
SDATA_IN0
SDATA_OUT0
05
79
8-
0
13
Figure 13. Default Program Signal Flow
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ADAU1761 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL
ADAU1761BCPZ 功能描述:IC SIGMADSP CODEC PLL 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:SigmaDSP® 標準包裝:2,500 系列:- 類型:PCM 數(shù)據(jù)接口:PCM 音頻接口 分辨率（位）:15 b ADC / DAC 數(shù)量:1 / 1 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):- 動態(tài)范圍，標準 ADC / DAC (db):- 電壓 - 電源，模擬:2.7 V ~ 3.3 V 電壓 - 電源，數(shù)字:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:80-VFBGA 供應商設(shè)備封裝:80-BGA MICROSTAR JUNIOR（5x5） 包裝:帶卷 (TR) 其它名稱:296-21257-2
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ADAU1761BCPZ-R7 功能描述:IC SIGMADSP CODEC PLL 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:SigmaDSP® 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
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