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| 型號： | ADAU1702JSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AUDIO PROC 2ADC/4DAC 48-LQFP |
| 標準包裝： | 1 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應(yīng)用： | 車載，監(jiān)視器，MP3 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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ADAU1702
Rev. C | Page 18 of 52
POWER REDUCTION MODES
Sections of the ADAU1702 chip can be turned on and off as
needed to reduce power consumption. These include the ADCs,
DACs, and voltage reference.
The individual analog sections can be turned off by writing to
the auxiliary ADC and power control register. By default, the
ADCs, DACs, and reference are enabled (all bits set to 0). Each
of these can be turned off by writing a 1 to the appropriate bits
in this register. The ADC power-down mode powers down both
ADCs, and each DAC can be powered down individually. The
current savings is about 15 mA when the ADCs are powered
down and about 4 mA for each DAC that is powered down.
The voltage reference, which is supplied to both the ADCs
and DACs, should only be powered down if all ADCs and
DACs are powered down. The reference is powered down by
setting both Bit 6 and Bit 7 of the control register.
USING THE OSCILLATOR
The ADAU1702 can use an on-board oscillator to generate
its master clock. The oscillator is designed to work with a
256 × fS master clock, which is 12.288 MHz for a fS of 48 kHz
and 11.2896 MHz for a fS of 44.1 kHz. The crystal in the oscil-
lator circuit should be an AT-cut, parallel resonator operating
at its fundamental frequency. Figure 14 shows the external
circuit recommended for proper operation.
C1
100
MCLKI
OSCO
C2
ADAU1702
05
79
8-
01
4
Figure 14. Crystal Oscillator Circuit
The 100 Ω damping resistor on OSCO gives the oscillator a
voltage swing of approximately 2.2 V. The crystal shunt capaci-
tance should be 7 pF. Its load capacitance should be about 18 pF,
although the circuit supports values of up to 25 pF. The necessary
values of the C1 and C2 load capacitors can be calculated from
the crystal load capacitance as follows:
stray
L
C
C2
C1
C2
C1
C
+
×
=
where Cstray is the stray capacitance in the circuit and is usually
assumed to be approximately 2 pF to 5 pF.
OSCO should not be used to drive the crystal signal directly to
another IC. This signal is an analog sine wave, and it is not appro-
priate to use it to drive a digital input. There are two options for
using the ADAU1702 to provide a master clock to other ICs in
the system. The first, and less recommended, method is to use a
high impedance input digital buffer on the OSCO signal. If this
approach is used, minimize the trace length to the buffer input.
The second method is to use a clock from the serial output port.
Pin MP11 can be set as an output (master) clock divided down
from the internal core clock. If this pin is set to serial output port
(OUTPUT_BCLK) mode in the multipurpose pin configuration
register (Address 2081) and the port is set to master in the serial
output control register (Address 2078), the desired output
frequency can also be set in the serial output control register
with the OBF[1:0] bits (see Table 47).
If the oscillator is not used in the design, it can be powered
down to save power. This can be done if a system master clock
is already available in the system. By default, the oscillator is
powered on. The oscillator powers down when a 1 is written to
the OPD bit of the oscillator power-down register (see Table 58).
SETTING MASTER CLOCK/PLL MODE
The MCLKI input of the ADAU1702 feeds a PLL, which generates
the 25 MIPS SigmaDSP core clock. In normal operation, the
input to MCLKI must be one of the following: 64 × fS, 256 × fS,
384 × fS, or 512 × fS, where fS is the input sampling rate. The
mode is set on PLL_MODE0 and PLL_MODE1 as described in
Table 11. If the ADAU1702 is set to receive double-rate signals
(by reducing the number of program steps per sample by a factor
of 2 using the core control register), the master clock frequency
must be 32 × fS, 128 × fS, 192 × fS, or 256 × fS. If the ADAU1702
is set to receive quad-rate signals (by reducing the number of
program steps per sample by a factor of 4 using the core control
register), the master clock frequency must be 16 × fS, 64 × fS, 96 × fS,
or 128 × fS. On power-up, a clock signal must be present on the
MCLKI pin so that the ADAU1702 can complete its
initialization routine.
Table 11. PLL Modes
MCLKI Input
PLL_MODE0
PLL_MODE1
64 × fS
0
256 × fS
0
1
384 × fS
1
0
512 × fS
1
Do not change the clock mode without also resetting the
ADAU1702. If the mode is changed during operation, a click or
pop can result in the output signals. Change the state of the
PLL_MODEx pins while holding RESET low.
Connect the PLL loop filter to the PLL_LF pin. This filter, shown
in Figure 15, includes three passive components—two capacitors
and a resistor. The values of these components do not need to
be exact; the tolerance can be up to 10% for the resistor and up
to 20% for the capacitors. The 3.3 V signal shown in Figure 15 can
be connected to the AVDD supply of the chip.
ADAU1702
3.3V
475
PLL_LF
56nF
3.3nF
05
79
8-
0
15
Figure 15. PLL Loop Filter
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| ADAU1702JSTZ-RL | 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
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| ADAU1761BCPZ-R7 | 功能描述:IC SIGMADSP CODEC PLL 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:SigmaDSP® 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
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