參數(shù)資料
型號(hào)： ADAU1702JSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 41/52頁
文件大?。?/td> 0K
描述： IC AUDIO PROC 2ADC/4DAC 48-LQFP
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
類型： 音頻處理器
應(yīng)用： 車載，監(jiān)視器，MP3
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
產(chǎn)品目錄頁面： 776 (CN2011-ZH PDF)
ADAU1702
Rev. C | Page 46 of 52
The serial data clocks need to be synchronous with the
ADAU1702 master clock input.
The input control register allows control of clock polarity and
data input modes. The valid data formats are I2S, left-justified,
right-justified (24-/20-/18-/16-bit), and 8-channel TDM. In all
modes, except for the right-justified modes, the serial port accepts
an arbitrary number of bits up to a limit of 24. Extra bits do not
cause an error, but they are truncated internally. Proper operation
of the right-justified modes requires that there be exactly 64 BCLKs
per audio frame. The TDM data is input on SDATA_IN0. The
LRCLK in TDM mode can be input to the ADAU1702 either as a
50/50 duty cycle clock or as a bit-wide pulse.
In TDM mode, the ADAU1702 can be a master for 48 kHz and
96 kHz data, but not for 192 kHz data. Table 62 lists the modes
in which the serial output port can function.
Table 62. Serial Output Port Master/Slave Mode Capabilities
fS
2-Channel Modes
(I2S, Left Justified,
Right Justified)
8-Channel TDM
48 kHz
Master and slave
96 kHz
Master and slave
192 kHz
Master and slave
Slave only
The output control registers allow the user to control clock
polarities, clock frequencies, clock types, and data format. In
all modes except for the right-justified modes (MSB delayed by
8, 12, or 16 bits), the serial port accepts an arbitrary number of
bits up to a limit of 24. Extra bits do not cause an error, rather,
they are truncated internally. Proper operation of the right-justified
modes requires the LSB to align with the edge of the LRCLK.
The default settings of all serial port control registers correspond
to the 2-channel I2S mode. All register settings apply to both
master and slave modes, unless otherwise noted.
The function of each multipurpose pin in serial data port mode
is listed in Table 63. Pin MP0 to Pin MP5 support digital data
input to the ADAU1702, and Pin MP6 to Pin MP11 handle digital
data output from the DSP. The configuration of the serial data
input port is set in the serial input control register (Table 49), and
the configuration of the corresponding output port is controlled
with the serial output control register (Table 47). The clocks of
the input port function only as slaves, whereas the output port
clocks can be set to function as either masters or slaves. The
INPUT_LRCLK (MP4) and INPUT_BCLK (MP5) pins are
used to clock the SDATA_INx (MP0 to MP3) signals, and the
OUTPUT_LRCLK (MP10) and OUTPUT_BCLK (MP11) pins
are used to clock the SDATA_OUTx (MP6 to MP9) signals.
If an external ADC is connected as a slave to the ADAU1702,
use both the input and output port clocks. The OUTPUT_LRCLK
(MP10) and OUTPUT_BCLK (MP11) pins must be set to master
mode and connected externally to the INPUT_LRCLK (MP4)
and INPUT_BCLK (MP5) pins, as well as to the external ADC
clock input pins. The data is output from the external ADC into
the SigmaDSP on one of the four SDATA_INx pins (MP0 to MP3).
Connections to an external DAC are handled exclusively with the
output port pins. The OUTPUT_LRCLK and OUTPUT_BCLK
pins can be set to function as either masters or slaves, and the
SDATA_OUTx pins are used to output data from the SigmaDSP
to the external DAC.
Table 64 describes the proper configurations for standard audio
data formats.
Table 63. Multipurpose Pin Serial Data Port Functions
Multipurpose Pin
Function
MP0
SDATA_IN0/TDM_IN
MP1
SDATA_IN1
MP2
SDATA_IN2
MP3
SDATA_IN3
MP4
INPUT_LRCLK (slave only)
MP5
INPUT_BCLK (slave only)
MP6
SDATA_OUT0/TDM_OUT
MP7
SDATA_OUT1
MP8
SDATA_OUT2
MP9
SDATA_OUT3
MP10
OUTPUT_LRCLK (master or slave)
MP11
OUTPUT_BCLK (master or slave)
Table 64. Data Format Configurations
Format
LRCLK Polarity
LRCLK
Type
BCLK Polarity
MSB Position
Frame begins on falling edge
Clock
Data changes on falling edge
Delayed from LRCLK edge
by 1 BCLK
Left Justified (Figure 33)
Frame begins on rising edge
Clock
Data changes on falling edge
Aligned with LRCLK edge
Right Justified (Figure 34)
Frame begins on rising edge
Clock
Data changes on falling edge
Delayed from LRCLK edge
by 8, 12, or 16 BCLKs
TDM with Clock (Figure 35)
Frame begins on falling edge
Clock
Data changes on falling edge
Delayed from start of word clock
by 1 BCLK
TDM with Pulse (Figure 36)
Frame begins on rising edge
Pulse
Data changes on falling edge
Delayed from start of word clock
by 1 BCLK
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