參數(shù)資料
型號(hào)： ADAU1702JSTZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 35/52頁(yè)
文件大?。?/td> 0K
描述： IC AUDIO PROC 2ADC/4DAC 48-LQFP
標(biāo)準(zhǔn)包裝： 2,000
系列： SigmaDSP®
類型： 音頻處理器
應(yīng)用： 車載，監(jiān)視器，MP3
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
ADAU1702
Rev. C | Page 40 of 52
ADDRESS 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER
Table 46. Serial Output Control Register Bit Map
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0
OLRP
OBP
M/S
OBF1
OBF0
OLF1
OLF0
FST
TDM
MSB2
MSB1
MSB0
OWL1
OWL0
0x0000
Table 47.
Bit Name
Description
OLRP
OUTPUT_LRCLK polarity. When this bit is set to 0, the left channel data is clocked when OUTPUT_LRCLK is low
and the right channel data is clocked when OUTPUT_LRCLK is high. When this bit is set to 1, the right channel
data is clocked when OUTPUT_LRCLK is low and the left channel data is clocked when OUTPUT_LRCLK is high.
OBP
OUTPUT_BCLK polarity. This bit controls on which edge of the bit clock the output data is clocked. Data
changes on the falling edge of OUTPUT_BCLK when this bit is set to 0, and it changes on the rising edge
when this bit is set to 1.
M/S
Master/slave. This bit sets whether the output port is a clock master or slave. The default setting is slave; on
power-up, the OUTPUT_BCLK and OUTPUT_LRCLK pins are set as inputs until this bit is set to 1, at which time
they become clock outputs.
OUTPUT_BCLK frequency (master mode only). When the output port is being used as a clock master, these
bits set the frequency of the output bit clock, which is divided down from an internal 1024 × fS clock (49.152 MHz
for a fS of 48 kHz).
Setting
Function
00
Internal clock/16
01
Internal clock/8
10
Internal clock/4
OBF[1:0]
11
Internal clock/2
OUTPUT_LRCLK frequency (master mode only). When the output port is used as a clock master, these bits set
the frequency of the output word clock on the OUTPUT_LRCLK pins, which is divided down from an internal
1024 × fS clock (49.152 MHz for a fS of 48 kHz).
Setting
Function
00
Internal clock/1024
01
Internal clock/512
10
Internal clock/256
OLF[1:0]
11
Reserved
FST
Frame sync type. This bit sets the type of signal on the OUTPUT_LRCLK pins. When this bit is set to 0, the
signal is a word clock with a 50% duty cycle; when this bit is set to 1, the signal is a pulse with a duration of
one bit clock at the beginning of the data frame.
TDM
TDM enable. Setting this bit to 1 changes the output port from four serial stereo outputs to a single 8-channel TDM
output stream on the SDATA_OUT0 pin (MP6).
MSB position. These three bits set the position of the MSB of data with respect to the LRCLK edge. The data
output of the ADAU1702 is always MSB first.
Setting
Function
000
Delay by 1
001
Delay by 0
010
Delay by 8
011
Delay by 12
100
Delay by 16
101
Reserved
MSB[2:0]
111
Reserved
Output word length. These bits set the word length of the output data-word. All bits following the LSB are set to 0.
OWL[1:0]
Setting
00
24 bits
01
20 bits
10
16 bits
OWL[1:0]
11
Reserved
相關(guān)PDF資料
PDF描述
ADAV4601BSTZ IC AUDIO CODEC PROCESSOR 80-LQFP
ADAV4622BSTZ IC AUD PRO ATV/SIF DECODE 80LQFP
ADCLK846BCPZ-REEL7 IC CLK BUFFER 1:6 1.2GHZ 24LFCSP
ADCLK854BCPZ IC CLOCK BUFFER MUX 2:12 48LFCSP
ADCLK907BCPZ-WP IC CLK/DATA BUFF DVR 1:1 16LFCSP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADAU1761 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL
ADAU1761BCPZ 功能描述:IC SIGMADSP CODEC PLL 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:PCM 數(shù)據(jù)接口:PCM 音頻接口 分辨率（位）:15 b ADC / DAC 數(shù)量:1 / 1 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):- 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):- 電壓 - 電源，模擬:2.7 V ~ 3.3 V 電壓 - 電源，數(shù)字:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:80-VFBGA 供應(yīng)商設(shè)備封裝:80-BGA MICROSTAR JUNIOR（5x5） 包裝:帶卷 (TR) 其它名稱:296-21257-2
ADAU1761BCPZ 制造商:Analog Devices 功能描述:IC, AUDIO CODEC, 24BIT, 96KHZ, LFCSP-32
ADAU1761BCPZ-R7 功能描述:IC SIGMADSP CODEC PLL 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
ADAU1761BCPZ-RL 功能描述:IC SIGMADSP CODEC PLL 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*