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參數(shù)資料
| 型號： | ADAU1702JSTZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AUDIO PROC 2ADC/4DAC 48-LQFP |
| 標準包裝： | 2,000 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應用： | 車載，監(jiān)視器，MP3 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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ADAU1702
Rev. C | Page 26 of 52
SPI PORT
By default, the ADAU1702 is in I2C mode, but it can be put into
SPI control mode by pulling CLATCH/WP low three times. The
SPI port uses a 4-wire interface, consisting of CLATCH, CCLK,
CDATA, and COUT signals, and is always a slave port. The
CLATCH signal should go low at the beginning of a transaction
and high at the end of a transaction. The CCLK signal latches
CDATA during a low-to-high transition. COUT data is shifted
out of the ADAU1702 on the falling edge of CCLK and should be
clocked into a receiving device, such as a microcontroller, on the
CCLK rising edge. The CDATA signal carries the serial input
data, and the COUT signal is the serial output data. The COUT
signal remains three-stated until a read operation is requested.
This allows other SPI-compatible peripherals to share the same
readback line. All SPI transactions have the same basic format
shown in Table 17. A timing diagram is shown in Figure 3. Write
all data MSB first. The ADAU1702 cannot be taken out of SPI
mode without a full reset.
Chip Address R/W
The first byte of an SPI transaction includes the 7-bit chip address
and a R/W bit. The chip address is set by the ADDR0 pin. This
allows two ADAU1702s to share a CLATCH signal, yet continue to
operate independently. When ADDR0 is low, the chip address is
0000000; when it is high, the address is 0000001 (see
The LSB of this first byte determines whether the SPI trans-
action is a read (Logic Level 1) or a write (Logic Level 0).
Table 16. ADAU1702 SPI Address Byte Format
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0
ADDR0
R/W
Subaddress
The 12-bit subaddress word is decoded into a location in one of
the memorie areas or registers. This subaddress is the location
of the appropriate RAM location or register. The MSBs of the
subaddress are zero padded to bring the word to a full two-byte
length.
Data Bytes
The number of data bytes varies according to the register or
memory being accessed. During a burst mode write, an initial
subaddress is written followed by a continuous sequence of data
for consecutive memory/register locations. The detailed data
format for continuous mode operation is shown in Table 21 and
Table 23 in the Read/Write Data Formats section.
A sample timing diagram for a single-write SPI operation to the
parameter RAM is shown in Figure 26. A sample timing diagram
of a single-read SPI operation is shown in Figure 27. The COUT
pin goes from three-state to being driven at the beginning of
Byte 3. In this example, Byte 0 to Byte 2 contain the addresses,
and the R/W bit and subsequent bytes carry the data.
Table 17. Generic Control Word Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4 1
CHIP_ADR[6:0], R/W
0000, SUBADR[11:8]
SUBADR[7:0]
Data
1 Continues to end of data.
CLATCH
CCLK
CDATA
BYTE 0
BYTE 1
BYTE 2
BYTE 3
05
79
8
-02
6
Figure 26. SPI Write to ADAU1702 Clocking (Single-Write Mode)
CLATCH
CCLK
CDATA
COUT
BYTE 0
BYTE 1
HIGH-Z
DATA
HIGH-Z
BYTE 2
05
79
8-
02
7
Figure 27. SPI Read from ADAU1702 Clocking (Single-Read Mode)
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