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| 型號： | ADAU1702JSTZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/52頁 |
| 文件大小： | 0K |
| 描述： | IC AUDIO PROC 2ADC/4DAC 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應(yīng)用： | 車載，監(jiān)視器，MP3 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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ADAU1702
Rev. C | Page 39 of 52
ADDRESS 2076 (0x081C)—DSP CORE CONTROL REGISTER
Table 44. DSP Core Control Register Bit Map
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
RSVD
GD1
GD0
RSVD
AACW
GPCW
IFCW
IST
ADM
DAM
CR
SR1
SR0
0x0000
Table 45. DSP Core Control Register
Bit Name
Description
GPIO debounce control. These bits set the debounce time of the multipurpose pins, which are set as GPIO inputs.
Setting
Time (ms)
00
20
01
40
10
GD[1:0]
11
5
AACW
Auxiliary ADC data registers control port write mode. Setting this bit allows data to be written directly to the
auxiliary ADC data registers (Address 2057 to Address 2060) from the control port. When this bit is set, the
auxiliary ADC data registers ignore the settings on the multipurpose pins.
GPCW
GPIO pin setting register control port write mode. When this bit is set, the GPIO pin setting register (Address 2056)
can be written to directly from the control port and this register ignores the input settings on the multi-
purpose pins.
IFCW
Interface registers control port write mode. When this bit is set, data can be written directly to the interface
registers (Address 2048 to Address 2055) from the control port. In that state, the interface registers are not
written from the SigmaDSP program.
IST
Initiate safeload transfer. Setting this bit to 1 initiates a safeload transfer to the parameter RAM. This bit is
automatically cleared when the operation is complete. There are five safeload register pairs (address/data);
only those registers that have been written since the last safeload event are transferred to the parameter RAM.
ADM
Mute ADCs. This bit mutes the output of the ADCs. The bit defaults to 0 and is active low; therefore, it must be
set to 1 to transmit audio signals from the ADCs.
DAM
Mute DACs. This bit mutes the output of the DACs. The bit defaults to 0 and is active low; therefore, it must be
set to 1 to transmit audio signals from the DACs.
CR
Clear internal registers to 0. This bit defaults to 0 and is active low. It must be set to 1 for a signal to pass
through the SigmaDSP core.
SR[1:0]
Sample rate. These bits set the number of DSP instructions for every sample and the sample rate at which the
ADAU1702 operates. At the default setting of 1×, there are 512 instructions per audio sample. This setting
should be used with sample rates such as 48 kHz and 44.1 kHz.
At the 2× setting, the number of instructions per frame is halved to 256 and the ADCs and DACs nominally run
at a 96 kHz sample rate.
At the 4× setting, there are 128 instructions per cycle and the converters run at a 192 kHz sample rate.
Setting
Function
00
1× (512 instructions)
01
2× (256 instructions)
10
4× (128 instructions)
11
Reserved
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| ADAU1761BCPZ-R7 | 功能描述:IC SIGMADSP CODEC PLL 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
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