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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ADAU1702JSTZ-RL |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 15/52闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC AUDIO PROC 2ADC/4DAC 48-LQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 2,000 |
| 绯诲垪锛� | SigmaDSP® |
| 椤炲瀷锛� | 闊抽牷铏曠悊鍣� |
| 鎳�(y墨ng)鐢細 | 杌婅級锛岀洠(ji膩n)瑕栧櫒锛孧P3 |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 48-LQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 48-LQFP锛�7x7锛� |
| 鍖呰锛� | 甯跺嵎 (TR) |
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ADAU1702
Rev. C | Page 22 of 52
CONTROL PORTS
The ADAU1702 can operate in one of three control modes:
I2C control
SPI control
Self-boot (no external controller)
The ADAU1702 has both a 4-wire SPI control port and a
2-wire I2C bus control port. Each can be used to set the RAMs
and registers. When the SELFBOOT pin is low at power-up, the
part defaults to I2C mode but can be put into SPI control mode
by pulling the CLATCH/WP pin low three times. When the
SELFBOOT pin is set high at power-up, the ADAU1702 loads
its program, parameters, and register settings from an external
EEPROM on startup.
The control port is capable of full read/write operation for all
addressable memory and registers. Most signal processing
parameters are controlled by writing new values to the parameter
RAM using the control port. Other functions, such as mute and
input/output mode control, are programmed by writing to the
registers.
All addresses can be accessed in a single address mode or a
burst mode. The first byte (Byte 0) of a control port write
contains the 7-bit chip address plus the R/W bit. The next two
bytes (Byte 1 and Byte 2) together form the subaddress of the
memory or register location within the ADAU1702. This
subaddress must be two bytes because the memory locations
within the ADAU1702 are directly addressable and their sizes
exceed the range of single byte addressing. All subsequent bytes
(starting with Byte 3) contain the data, such as control port data,
program data, or parameter data. The number of bytes per word
depends on the type of data that is being written. The exact formats
for specific types of writes are shown in
.
The ADAU1702 has several mechanisms for updating signal
processing parameters in real time without causing pops or
clicks. If large blocks of data need to be downloaded, the output
of the DSP core can be halted (using the CR bit in the DSP core
control register (Address 2076)), new data can be loaded, and
then the device can be restarted. This is typically done during
the booting sequence at startup or when loading a new program
into RAM. In cases where only a few parameters need to be
changed, they can be loaded without halting the program. To
avoid unwanted side effects while loading parameters on the fly, the
SigmaDSP provides safeload registers. The safeload registers can
be used to buffer a full set of parameters (for example, the five
coefficients of a biquad) and then transfer these parameters into
the active program within one audio frame. The safeload mode
uses internal logic to prevent contention between the DSP core
and the control port.
The control port pins are multifunctional, depending on the
mode in which the part is operating. Table 13 details these
multiple functions.
Table 13. Control Port Pins and SELFBOOT Pin Functions
Pin
I2C Mode
SPI Mode
Self-Boot
SCL/CCLK
SCL鈥攊nput
CCLK鈥攊nput
SCL鈥攐utput
SDA/COUT
SDA鈥攐pen-collector output
COUT鈥攐utput
SDA鈥攐pen-collector output
ADDR1/CDATA/WB
ADDR1鈥攊nput
CDATA鈥攊nput
WB鈥攚riteback trigger
CLATCH/WP
Unused input鈥攖ie to ground or IOVDD
CLATCH鈥攊nput
WP鈥擡EPROM write protect, open-collector output
ADDR0
ADDR0鈥攊nput
Unused input鈥攖ie to ground or IOVDD
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ADAU1761 | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL |
| ADAU1761BCPZ | 鍔熻兘鎻忚堪:IC SIGMADSP CODEC PLL 32LFCSP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 绶ㄨВ纰煎櫒 绯诲垪:SigmaDSP® 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:- 椤炲瀷:PCM 鏁�(sh霉)鎿�(j霉)鎺ュ彛:PCM 闊抽牷鎺ュ彛 鍒嗚鲸鐜囷紙浣嶏級:15 b ADC / DAC 鏁�(sh霉)閲�:1 / 1 涓夎绌嶅垎瑾�(di脿o)璁�:鏄� S/N 姣旓紝妯�(bi膩o)婧�(zh菙n) ADC / DAC (db):- 鍕曟厠(t脿i)鑼冨湇锛屾(bi膩o)婧�(zh菙n) ADC / DAC (db):- 闆诲 - 闆绘簮锛屾ā鎿�:2.7 V ~ 3.3 V 闆诲 - 闆绘簮锛屾暩(sh霉)瀛�:2.7 V ~ 3.3 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:80-VFBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:80-BGA MICROSTAR JUNIOR锛�5x5锛� 鍖呰:甯跺嵎 (TR) 鍏跺畠鍚嶇ū:296-21257-2 |
| ADAU1761BCPZ | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:IC, AUDIO CODEC, 24BIT, 96KHZ, LFCSP-32 |
| ADAU1761BCPZ-R7 | 鍔熻兘鎻忚堪:IC SIGMADSP CODEC PLL 32LFCSP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 绶ㄨВ纰煎櫒 绯诲垪:SigmaDSP® 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:- 椤炲瀷:绔嬮珨鑱查煶闋� 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶 鍒嗚鲸鐜囷紙浣嶏級:18 b ADC / DAC 鏁�(sh霉)閲�:2 / 2 涓夎绌嶅垎瑾�(di脿o)璁�:鏄� S/N 姣�锛屾(bi膩o)婧�(zh菙n) ADC / DAC (db):81.5 / 88 鍕曟厠(t脿i)鑼冨湇锛屾(bi膩o)婧�(zh菙n) ADC / DAC (db):82 / 87.5 闆诲 - 闆绘簮锛屾ā鎿�:2.6 V ~ 3.3 V 闆诲 - 闆绘簮锛屾暩(sh霉)瀛�:1.7 V ~ 3.3 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:48-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:48-TQFN-EP锛�7x7锛� 鍖呰:甯跺嵎 (TR) |
| ADAU1761BCPZ-RL | 鍔熻兘鎻忚堪:IC SIGMADSP CODEC PLL 32LFCSP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 绶ㄨВ纰煎櫒 绯诲垪:SigmaDSP® 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:- 椤炲瀷:绔嬮珨鑱查煶闋� 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶 鍒嗚鲸鐜囷紙浣嶏級:18 b ADC / DAC 鏁�(sh霉)閲�:2 / 2 涓夎绌嶅垎瑾�(di脿o)璁�:鏄� S/N 姣�锛屾(bi膩o)婧�(zh菙n) ADC / DAC (db):81.5 / 88 鍕曟厠(t脿i)鑼冨湇锛屾(bi膩o)婧�(zh菙n) ADC / DAC (db):82 / 87.5 闆诲 - 闆绘簮锛屾ā鎿�:2.6 V ~ 3.3 V 闆诲 - 闆绘簮锛屾暩(sh霉)瀛�:1.7 V ~ 3.3 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:48-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:48-TQFN-EP锛�7x7锛� 鍖呰:甯跺嵎 (TR) |
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