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| 型號： | ADAU1702JSTZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AUDIO PROC 2ADC/4DAC 48-LQFP |
| 標準包裝： | 2,000 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應用： | 車載，監(jiān)視器，MP3 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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ADAU1702
Rev. C | Page 30 of 52
RAMS AND REGISTERS
Table 19. RAM Map and Read/Write Modes
Memory
Size
Address Range
Read
Write
Write Modes
Parameter RAM
1024 × 32
0 to 1023 (0x0000 to 0x03FF)
Yes
Direct write 1 safeload write
Program RAM
512 × 40
1024 to 1535 (0x0400 to 0x05FF)
Yes
Direct write1
Reserved
Not applicable
1536 to 2047 (0x0600 to 0x07FF) 2
No
Not applicable
1 Internal registers should be cleared first to avoid clicks/pops.
2 Addresses 1536 to 2047 (0x0600 to 0x07FF) are reserved RAM locations and data cannot be written to them.
ADDRESS MAPS
ADAU1702 register map. The address space encompasses a
set of registers and two RAMs: one holds signal processing
parameters and the other holds the program instructions. The
program RAM and parameter RAM are initialized on power-up
from on-board boot ROMs (see the Power-Up Sequence section).
All RAMs and registers have a default value of all 0s, except for
the program RAM, which is loaded with the default program
(see the Initialization section).
PARAMETER RAM
The parameter RAM is 32 bits wide and occupies Address 0
to Address 1023. Each parameter is padded with four 0s before
parameter RAM is initialized to all 0s on power-up. The data
format of the parameter RAM is twos complement, 5.23.
This means that the coefficients can range from +16.0 (minus
1 LSB) to 16.0, with 1.0 represented by the binary word,
0000 1000 0000 0000 0000 0000 0000, or by the hexadecimal
word, 0x00 0x80 0x00 0x00.
The parameter RAM can be written using one of the two
following methods: a direct read/write or a safeload write.
Direct Read/Write
The direct read/write method allows direct access to the program
RAM and parameter RAM. This mode of operation is typically
used when loading a new RAM using burst mode addressing. The
clear registers bit in the core control register should be set to 0
using this mode to prevent any clicks or pops in the outputs. Note
that this mode can be used during live program execution, but
because there is no handshaking between the core and the control
port, the parameter RAM is unavailable to the DSP core during
control writes, resulting in clicks and pops in the audio stream.
Safeload Write
Up to five safeload registers can be loaded with the parameter
RAM address and data. The data is then transferred to the
requested address when the RAM is not busy. This method can
be used for dynamic updates while live program material is
playing through the ADAU1702. For example, a complete
update of one biquad section can occur in one audio frame
while the RAM is not busy. This method is not available for
writing to the program RAM or control registers.
DATA RAM
The ADAU1702 data RAM is used to store audio data-words for
processing. For the most part, this process is transparent to the
user. The user cannot address this RAM space, which has a size
of 0.5k words, directly from the control port.
Data RAM utilization should be considered when implementing
blocks that require large amounts of data RAM space, such as
delays. The SigmaDSP core processes delay times in one sample
increments; therefore, the total pool of delay available to the user
equals 512 multiplied by the sample period. For a fS of 48 kHz,
the pool of available delay is a maximum of about 10 ms. In
practice, this much data memory is not available to the user
because every block in a design uses a few data memory locations
for its processing. In most DSP programs, this does not signifi-
cantly impact the total delay time. The SigmaStudio compiler
manages the data RAM and indicates if the number of addresses
needed in the design exceeds the maximum available.
READ/WRITE DATA FORMATS
The read/write formats of the control port are designed to
be byte oriented. This allows easy programming of common
microcontroller chips. To fit into a byte oriented format, 0s are
appended to the data fields before the MSB to extend the data-
word to eight bits. For example, 28-bit words written to the
parameter RAM are appended with four leading 0s to equal
32 bits (four bytes); 40-bit words written to the program RAM
are not appended with 0s because they are already a full five bytes.
These zero padded data fields are appended to a 3-byte field
consisting of a 7-bit chip address, a read/write bit, and an 11-bit
RAM/register address. The control port knows how many data
bytes to expect based on the address given in the first three bytes.
The total number of bytes for a single location write command
can vary from four bytes (for a control register write) to eight
bytes (for a program RAM write). Burst mode can be used to fill
contiguous register or RAM locations. A burst mode write begins
by writing the address and data of the first RAM or register location
to be written. Rather than ending the control port transaction
(by issuing a stop command in I2C mode or by bringing the
CLATCH signal high in SPI mode after the data-word), as is
done in a single address write, the next data-word can be
immediately written without specifying its address. The
ADAU1702 control port auto-increments the address of each write
even across the boundaries of the different RAMs and registers.
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