參數(shù)資料
型號(hào)： ADAU1442YSVZ-3A
廠商： Analog Devices Inc
文件頁數(shù)： 14/93頁
文件大小： 0K
描述： IC SIGMADSP 28B 175MHZ 100TQFP
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
類型： 音頻處理器
應(yīng)用： 車載音頻
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
ADAU1442/ADAU1445/ADAU1446
Data Sheet
Rev. D | Page 20 of 92
INITIALIZATION
Power-Up Sequence
The ADAU1442/ADAU1445/ADAU1446 have a built-in initiali-
zation period, which allows sufficient time for the PLL to lock
and the registers to initialize their values. On a positive edge of
RESET, the PLL settings are immediately set by the PLL0, PLL1,
and PLL2 pins, and the master clock signal is blocked from the
chip subsystems. The initialization time, which is measured from
the rising edge of RESET, is dependent on the frequency of the
signal input to the XTALI pin, or fXTALI. The total initialization time is
1/(fXTALI/D) × 215 sec
where D is the PLL divider, as set by the PLL0, PLL1, and PLL2
pins. The PLL divider settings are described in Table 9.
For example, if the signal input to XTALI has a frequency of
12.288 MHz and the PLL divider is set to 4 (PLL = 0, PLL1 = 1,
and PLL2 = 0), the initialization time lasts
1/(12288000/4) × 215 sec = 0.010667 sec (or 10.667 ms)
New values should not be written via the control port until the
initialization is complete.
Table 8 shows some typical times to boot the ADAU1442/
ADAU1445/ADAU1446 into the operational state necessary for an
application, assuming that a 400 kHz I2C clock or a 5 MHz SPI
clock is used and a full program, parameter set, and all registers
(9 kB) are loaded. In reality, most applications use less than this full
amount, and unused program and parameter RAM need not be
initialized; therefore, the total boot time may be shorter.
Recommended Program/Parameter Loading Procedure
When writing large amounts of data to the program or parameter
RAM in direct write mode, such as when downloading the initial
contents of the RAMs from an external memory, the processor core
should be disabled to prevent unpleasant noises from appearing
at the audio output. When small amounts of data are transmitted
during real-time operation of the DSP, such as when updating
individual parameters, the software safeload mechanism can be
used. More information is available in the Software Safeload
section.
Power-Reduction Modes
Sections of the ADAU1442/ADAU1445/ADAU1446 chips can be
turned on and off as needed to reduce power consumption.
These include the ASRCs, S/PDIF receiver and transmitter,
auxiliary ADCs, and DSP core. More information is available in
System Initialization Sequence
Before the IC can process audio in the DSP, the following initial-
ization sequence must be completed. (Step 5 through Step 11
can be performed in any order, as needed.)
1. Power on the IC and bring it out of reset. The order of the
power supplies (DVDD, IOVDD, and AVDD) does not matter.
2. Wait at least 10.667 ms for the initialization to complete if the
XTALI input is 12.288 MHz and the PLL divider is set to 4
(see the Power-Up Sequence section for information about
calculating the initialization time if another fXTALI is used).
3. Enable the master clocks of all modules to be used (see the
4. Set the DSP core rate select register (0xE220) to 0x001C.
This disables the start pulse to the core.
5. Deassert the core run bit (see the DSP Core Modes and
Settings section).
6. Set the serial input modes (see the Serial Input Port Modes
7. Set the serial output modes (see the Serial Output Port
section).
8. Set the routing matrix modes (see details of Address 0xE080
to Address 0xE09B in the Flexible Audio Routing Matrix
Modes section).
9. Write the parameter RAM (Address 0x0000 to Address
0x0FFF).
10. Write the program RAM (Address 0x2000 to Address
0x2FFF).
11. Write the nonmodulo data RAM (Addresses vary based on
the SigmaStudio project file).
12. Write all other necessary control registers, such as ASRCs
and S/PDIF (Address 0xE221 to Address 0xE24C).
13. Set the DSP core rate select register (0xE220) to the desired
value. This enables the start pulse to the core. Table 12
contains a list of valid settings.
14. Assert the core run bit (see the DSP Core Modes and
Settings section).
Table 8. Power-Up Time
PLL Lock Time (ms)
(fXTALI = 12.288 MHz,
PLL Divider = 4)
Approximate Boot Time; Loading Maximum Program/Parameter/Registers (ms)
Total (ms)
I2C (at 400 kHz SCL)
SPI (at 5 MHz CCLK)
SPI (at 25 MHz CCLK)
10.667
25
2
0.4
11.067 to 35.667
相關(guān)PDF資料
PDF描述
VI-B6Z-MW CONVERTER MOD DC/DC 2V 40W
VI-233-CU-F1 CONVERTER MOD DC/DC 24V 200W
ADAU1445YSVZ-3A IC SIGMADSP 175MHZ 100TQFP
VI-232-IW-S CONVERTER MOD DC/DC 15V 100W
AD1941YSTZ IC DSP AUDIO 16CHAN 28BIT 48LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADAU1442YSVZ-3A-RL 功能描述:IC SIGMADSP 28B 175MHZ 100TQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1445YSVZ-3A 功能描述:IC SIGMADSP 175MHZ 100TQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1445YSVZ-3A-RL 功能描述:IC SIGMADSP 175MHZ 100TQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1446EBZ 制造商:Analog Devices 功能描述:SIGMADSP? DIGITAL AUDIO PROCESSOR WITH FLEXIBLE AUDIO - Bulk
ADAU1446YSTZ-3A 功能描述:IC SIGMADSP 175MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*