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參數(shù)資料
| 型號： | ADAU1442YSVZ-3A-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 65/93頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SIGMADSP 28B 175MHZ 100TQFP |
| 標準包裝： | 1,000 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應用： | 車載音頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應商設備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADAU1442/ADAU1445/ADAU1446
Rev. D | Page 67 of 92
Auxiliary Outputs—Set Enable Mode Register
(Address 0xE0C8)
Table 59. Bit Descriptions of Register 0xE0C8
Bit
Position
Description
Default
[15:2]
Reserved
[1:0]
Auxiliary outputs enable mode
01
00 = auxiliary outputs are always off.
01 = auxiliary outputs are always on.
10 = auxiliary outputs are off on reset.
(They switch on as soon as the hot enable
bit is 1 and switch off as soon as the S/PDIF
lock bit is 0.)
This register controls when the S/PDIF stream is active on the
multipurpose pins when the S/PDIF to I2S mode is active. For
more information, see the Enable S/PDIF to I2S Output section.
Setting Bits[1:0] of Register 0xE0C8 to 10 (auxiliary outputs are
off on reset) is useful for situations in which the S/PDIF stream
may be interrupted unexpectedly. An interruption causes the
S/PDIF lock bit to go low, which in turn disables the auxiliary
outputs. When the S/PDIF stream is recovered, the hot enable
bit must be activated to restore the auxiliary outputs (see the Set
Hot Enable Register (Address 0xE0CA) section for more
information).
S/PDIF Lock Bit Detection Register (Address 0xE0C9)
Table 60. Bit Descriptions of Register 0xE0C9
Bit
Position
Description
[15:1]
Reserved
0
S/PDIF input lock bit (read only)
0 = no valid input stream
1 = successful lock to input stream
This read-only register shows the status of the S/PDIF input
lock bit.
Set Hot Enable Register (Address 0xE0CA)
Table 61. Bit Descriptions of Register 0xE0CA
Bit
Position
Description
Default
[15:1]
Reserved
0
Hot enable bit
0
0 = hot enable inactive
1 = hot enable active
This register allows the hot enable bit to be set, which restarts the
auxiliary outputs when they are configured so that the auxiliary
outputs are off on a reset (that is, Bits[1:0] of Register 0xE0C8 are
set to 10). The hot enable bit is set to 0 automatically in the event
that the S/PDIF receiver loses lock. For more information, see the
(Address 0xE0C8) section.
Read Enable Auxiliary Output Register (Address 0xE0CB)
Table 62. Bit Descriptions of Register 0xE0CB
Bit
Position
Description
[15:1]
Reserved
0
Read enable auxiliary output (read only)
0 = S/PDIF auxiliary outputs disabled
1 = S/PDIF auxiliary outputs enabled
This read-only register shows the status of the S/PDIF auxiliary
outputs.
S/PDIF Loss-of-Lock Behavior Register (Address 0xE0CC)
Table 63. Bit Descriptions of Register 0xE0CC
Bit
Position
Description
Default
[15:1]
Reserved
0
S/PDIF loss-of-lock behavior
0
0 = S/PDIF disable on loss of lock
1 = S/PDIF ignore loss of lock
This register controls the behavior of the S/PDIF receiver in the
event of a loss of lock to the input stream. A loss of lock can arise
when there is severe noise or jitter on the S/PDIF input stream,
rendering it unrecognizable to the receiver. In the default mode,
such an event disables the S/PDIF receiver, causing it to stop
outputting frame sync pulses. This in turn causes the target
ASRC to be muted. Frame sync pulses do not resume until lock
is regained.
When the register is set to 1, the S/PDIF receiver always outputs
frame sync pulses, even if the integrity of the S/PDIF stream is
compromised and the audio samples cannot be recovered. In
such a case, the S/PDIF receiver data output remains at 0 until
lock is regained.
The S/PDIF receiver is robust and can recover streams with
integrity well below the standards of the AES/EBU specification.
Therefore, even in cases of extreme signal degradation, this
register should be used only when audio recovery is required.
In general, a loss-of-lock event is much shorter than an ASRC
mute or unmute ramp.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| ADAU1445YSVZ-3A | 功能描述:IC SIGMADSP 175MHZ 100TQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應商設備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| ADAU1445YSVZ-3A-RL | 功能描述:IC SIGMADSP 175MHZ 100TQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應商設備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| ADAU1446EBZ | 制造商:Analog Devices 功能描述:SIGMADSP? DIGITAL AUDIO PROCESSOR WITH FLEXIBLE AUDIO - Bulk |
| ADAU1446YSTZ-3A | 功能描述:IC SIGMADSP 175MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應商設備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| ADAU1446YSTZ-3A-RL | 功能描述:IC SIGMADSP 175MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應商設備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
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