參數(shù)資料
型號： AD9995KCPZRL
廠商： Analog Devices Inc
文件頁數(shù)： 56/60頁
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROCESSOR 56-LFCSP
標(biāo)準(zhǔn)包裝： 2,500
類型： CCD 信號處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 30mA
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 帶卷 (TR)
AD9995
–6–
PIN CONFIGURATION
TOP VIEW
AD9995
PIN 1
IDENTIFIER
42 SDI
41 SL
40 REFB
39 REFT
38 AVSS
37 CCDIN
36 AVDD
35 CLI
34 CLO
33 TCVDD
D5 1
D6 2
D7 3
D8 4
D9 5
D10 6
(MSB) D11 7
DRVDD 8
DRVSS 9
VSUB 10
56
D4
55
D3
54
D2
53
D1
52
D0
(LSB)
51
DCLK
50
HD
49
DVDD
48
DVSS
47
VD
V4
15
V5
16
V6
17
VSG1
18
VSG2
19
VSG3
2
0
VSG4
21
VSG5
22
H1
23
H2
24
SUBCK 11
V1 12
V2 13
V3 14
HVSS
25
HVDD
26
H3
27
H4
28
32 TCVSS
31 RGVDD
30 RG
29 RGVSS
46
SYNC_CL
P
45
STROBE
44
MSHUT
43
SCK
Pin
Mnemonic Type2 Description
1
D5
DO
Data Output
2
D6
DO
Data Output
3
D7
DO
Data Output
4
D8
DO
Data Output
5
D9
DO
Data Output
6
D10
DO
Data Output
7
D11
DO
Data Output (MSB)
8
DRVDD
P
Data Output Driver Supply
9
DRVSS
P
Data Output Driver Ground
10
VSUB
DO
CCD Substrate Bias
11
SUBCK
DO
CCD Substrate Clock (E-Shutter)
12
V1
DO
CCD Vertical Transfer Clock 1
13
V2
DO
CCD Vertical Transfer Clock 2
14
V3
DO
CCD Vertical Transfer Clock 3
15
V4
DO
CCD Vertical Transfer Clock 4
16
V5
DO
CCD Vertical Transfer Clock 5
17
V6
DO
CCD Vertical Transfer Clock 6
18
VSG1
DO
CCD Sensor Gate Pulse 1
19
VSG2
DO
CCD Sensor Gate Pulse 2
20
VSG3
DO
CCD Sensor Gate Pulse 3
21
VSG4
DO
CCD Sensor Gate Pulse 4
22
VSG5
DO
CCD Sensor Gate Pulse 5
23
H1
DO
CCD Horizontal Clock 1
24
H2
DO
CCD Horizontal Clock 2
25
HVSS
P
H1–H4 Driver Ground
26
HVDD
P
H1–H4 Driver Supply
27
H3
DO
CCD Horizontal Clock 3
28
H4
DO
CCD Horizontal Clock 4
29
RGVSS
P
RG Driver Ground
30
RG
DO
CCD Reset Gate Clock
31
RGVDD
P
RG Driver Supply
32
TCVSS
P
Analog Ground for Timing Core
33
TCVDD
P
Analog Supply for Timing Core
34
CLO
DO
Clock Output for Crystal
35
CLI
DI
Reference Clock Input
Pin
Mnemonic Type2 Description
36
AVDD
P
Analog Supply for AFE
37
CCDIN
AI
CCD Signal Input
38
AVSS
P
Analog Ground for AFE
39
REFT
AO
Voltage Reference Top Bypass
40
REFB
AO
Voltage Reference Bottom Bypass
41
SL
DI
3-Wire Serial Load Pulse
42
SDI
DI
3-Wire Serial Data Input
43
SCK
DI
3-Wire Serial Clock
44
MSHUT
DO
Mechanical Shutter Pulse
45
STROBE
DO
Strobe Pulse
46
SYNC
DI
External System Sync Input
47
VD
DIO
Vertical Sync Pulse
(Input for Slave Mode,
Output for Master Mode)
48
DVSS
P
Digital Ground
49
DVDD
P
Power Supply for VSG,V1–V6,
HD/VD, MSHUT, STROBE,
SYNC, and Serial Interface
50
HD
DIO
Horizontal Sync Pulse
(Input for Slave Mode, Output for
Master Mode)
51
DCLK
DO
Data Clock Output
52
D0
DO
Data Output (LSB)
53
D1
DO
Data Output
54
D2
DO
Data Output
55
D3
DO
Data Output
56
D4
DO
Data Output
NOTES
1See Figure 38 for circuit configuration.
2AI = Analog Input, AO = Analog Output, DI = Digital Input,
DO = Digital Output, DIO = Digital Input/Output, P = Power.
PIN FUNCTION DESCRIPTIONS1
REV. 0
OBSOLETE
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