參數(shù)資料
型號(hào)： AD9995KCPZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 36/60頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROCESSOR 56-LFCSP
標(biāo)準(zhǔn)包裝： 2,500
類型： CCD 信號(hào)處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 30mA
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 帶卷 (TR)
AD9995
–41–
Table XIX.Timing Core Register Map
Data Bit Default
Address Content Value
Register Name
Register Description
30
[0]
0
CLIDIVIDE
Divide CLI Input Clock by 2. 1 = Divide by 2.
31
[12:0]
01001
H1CONTROL
H1 Signal Control: Polarity [0](0 = Inversion, 1 = No Inversion).
H1 Positive Edge Location [6:1]. H1 Negative Edge Location [12:7].
32
[12:0]
01001
H3CONTROL
H3 Signal Control: Polarity [0](0 = Inversion, 1 = No Inversion).
H3 Positive Edge Location [6:1]. H3 Negative Edge Location [12:7].
33
[12:0]
00801
RGCONTROL
RG Signal Control: Polarity [0](0 = Inversion, 1 = No Inversion).
RG Positive Edge Location [6:1]. RG Negative Edge Location [12:7].
34
[1:0]
0
HBLKRETIME
Retime HBLK to Internal H1/H3 Clocks. H1 Retime [0]. H3 Retime [1].
Preferred setting is 1 for each bit. Setting each bit to 1 will add one cycle delay
to HBLK toggle positions.
35
[14:0]
1249
DRVCONTROL
Drive Strength Control for H1 [2:0], H2 [5:3], H3 [8:6], H4 [11:9], and
RG [14:12]. Drive Current Values: 0 = Off, 1 = 4.3 mA, 2 = 8.6 mA,
3 = 12.9 mA, 4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA.
36
[11:0]
00024
SAMPCONTROL
SHP/SHD Sample Control: SHP Sampling Location [5:0].
SHD Sampling Location [11:6].
37
[8:0]
100
DOUTCONTROL
DOUT Phase Control [5:0]. DCLK Mode [6]. DOUTDELAY [8:7].
Table XX. CLPOB Masking Register Map
Data Bit Default
Address Content Value
Register Name
Register Description
40
[23:0]
FFFFFF CLPMASK01
CLPOB Line Masking. Line #0 [11:0]. Line #1 [23:0].
41
[23:0]
FFFFFF CLPMASK23
CLPOB Line Masking. Line #2 [11:0]. Line #3 [23:0].
42
[11:0]
FFFFFF CLPMASK4
CLPOB Line Masking. Line #4 [11:0].
Table XXI. SG Pattern Register Map
Data Bit Default
Address Content Value
Register Name
Register Description
50
[3:0]
F
SGPOL
Start Polarity for SG Patterns. Pattern #0 [0]. Pattern #1 [1].
Pattern #2 [2]. Pattern #3 [3].
51
[23:0]
FFFFFF SGTOG12_0
Pattern #0.Toggle Position 1 [11:0].Toggle Position 2 [23:12].
52
[23:0]
FFFFFF SGTOG12_1
Pattern #1.Toggle Position 1 [11:0].Toggle Position 2 [23:12].
53
[23:0]
FFFFFF SGTOG12_2
Pattern #2.Toggle Position 1 [11:0].Toggle Position 2 [23:12].
54
[23:0]
FFFFFF SGTOG12_3
Pattern #3.Toggle Position 1 [11:0].Toggle Position 2 [23:12].
Table XXII. Shutter Control Register Map
Data Bit Default
Address Content Value
Register Name
Register Description
60
[4:0]
0
TRIGGER
Trigger for VSUB [0], MSHUT [1], STROBE [2], Exposure [3], and
Readout [4]. Note that to trigger the readout to automatically occur after the
exposure period, both exposure and readout should be triggered together.
61
[2:0]
2
READOUT
Number of Fields to Suppress the SUBCK Pulses after the VSG Line.
62
[11:0]
0
EXPOSURE
Number of Fields to Suppress the SUBCK and VSG Pulses.
[12]
0
VDHDOFF
Set = 1 to disable the VD/HD outputs during exposure (when >1 field).
63
[11:0]
0
SUBCKSUPPRESS
Number of SUBCK Pulses to Suppress after VSG Line.
[23:12]
0
SUBCKNUM
Number of SUBCK Pulses per Field.
64
[0]
1
SUBCKPOL
SUBCK Pulse Start Polarity.
65
[23:0]
FFFFFF SUBCK1TOG
First SUBCK Pulse.Toggle Position 1 [11:0].Toggle Position 2 [23:0].
66
[23:0]
FFFFFF SUBCK2TOG
Second SUBCK Pulse.Toggle Position 1 [11:0].Toggle Position 2 [23:0].
REV. 0
OBSOLETE
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