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| 型號： | AD9991KCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/60頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| 標準包裝： | 1 |
| 類型： | CCD 信號處理器，10 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9991
–13–
HORIZONTAL CLAMPING AND BLANKING
The AD9991’s horizontal clamping and blanking pulses are fully
programmable to suit a variety of applications. Individual control
is provided for CLPOB, PBLK, and HBLK during the different
regions of each eld. This allows the dark pixel clamping and
blanking patterns to be changed at each stage of the readout in
order to accommodate different image transfer timing and high
speed line shifts.
Individual CLPOB and PBLK Patterns
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 9. These two signals are independently pro-
grammed using the registers in Table III. SPOL is the start
polarity for the signal, and TOG1 and TOG2 are the rst and
second toggle positions of the pulse. Both signals are active low
and should be programmed accordingly.
A separate pattern for CLPOB and PBLK may be programmed
for each 10 V-sequence. As described in the Vertical Timing Gen-
eration section, up to 10 separate V-sequences can be created,
each containing a unique pulse pattern for CLPOB and PBLK.
Figure 9 shows how the sequence change positions divide the
readout eld into different regions. A different V-Sequence can be
assigned to each region, allowing the CLPOB and PBLK signals
to be changed accordingly with each change in the vertical timing.
Individual HBLK Patterns
The HBLK programmable timing shown in Figure 10 is simi-
lar to CLPOB and PBLK. However, there is no start polarity
control. Only the toggle positions are used to designate the start
and stop positions of the blanking period. Additionally, there is a
polarity control HBLKMASK that designates the polarity of the
horizontal clock signals H1–H4 during the blanking period. Set-
ting HBLKMASK high will set H1 = H3 = Low and H2 = H4 =
High during the blanking, as shown in Figure 11. As with the
CLPOB and PBLK signals, HBLK registers are available in each
V-sequence, allowing different blanking signals to be used with
different vertical timing sequences.
(3)
(2)
(1)
HD
CLPOB
PBLK
. . .
NOTES
PROGRAMMABLE SETTINGS:
(1) START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW)
(2) FIRST TOGGLE POSITION
(3) SECOND TOGGLE POSITION
. . .
ACTIVE
Figure 9. Clamp and Pre-Blank Pulse Placement
Table III. CLPOB and PBLK Pattern Registers
Register
Length
Range
Description
SPOL
1b
High/Low
Starting Polarity of CLPOB/PBLK for V-Sequence 0–9
TOG1
12b
0–4095 Pixel Location
First Toggle Position within Line for V-Sequence 0–9
TOG2
12b
0–4095 Pixel Location
Second Toggle Position within Line for V-Sequence 0–9
Table IV. HBLK Pattern Registers
Register
Length
Range
Description
HBLKMASK
1b
High/Low
Masking Polarity for H1/H3 (0 = H1/H3 Low, 1 = H1/H3 High)
HBLKALT
2b
0–3 Alternation Mode
Enables Odd/Even Alternation of HBLK Toggle Positions 0 =
Disable Alternation. 1 = TOG1–TOG2 Odd, TOG3–TOG6 Even.
2 = 3 = TOG1–TOG2 Even, TOG3–TOG6 Odd
HBLKTOG1
12b
0–4095 Pixel Location
First Toggle Position within Line for Each V-Sequence 0–9
HBLKTOG2
12b
0–4095 Pixel Location
Second Toggle Position within Line for Each V-Sequence 0–9
HBLKTOG3
12b
0–4095 Pixel Location
Third Toggle Position within Line for Each V-Sequence 0–9
HBLKTOG4
12b
0–4095 Pixel Location
Fourth Toggle Position within Line for Each V-Sequence 0–9
HBLKTOG5
12b
0–4095 Pixel Location
Fifth Toggle Position within Line for Each V-Sequence 0–9
HBLKTOG6
12b
0–4095 Pixel Location
Sixth Toggle Position within Line for Each V-Sequence 0–9
REV. 0
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| AD9991KCPZRL | 功能描述:IC CCD SIGNAL PROCESSOR 56-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9992 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
| AD9992_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
| AD9992BBCZ | 功能描述:IC CCD SGNL PROC 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9992BBCZRL | 功能描述:IC CCD SGNL PROC 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
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