參數(shù)資料
型號(hào)： AD9991KCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 30/60頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROCESSOR 56-LFCSP
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： CCD 信號(hào)處理器，10 位
輸入類(lèi)型： 邏輯
輸出類(lèi)型： 邏輯
接口： 3 線(xiàn)串口
安裝類(lèi)型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 帶卷 (TR)
AD9991
–36–
CIRCUIT LAYOUT INFORMATION
The AD9991 typical circuit connection is shown in Figure 38.
The PCB layout is critical in achieving good image quality from
the AD999x products. All of the supply pins, particularly the
AVDD1, TCVDD, RGVDD, and HVDD supplies, must be
decoupled to ground with good quality high frequency chip ca-
pacitors. The decoupling capacitors should be located as close
as possible to the supply pins, and should have a very low im-
pedance path to a continuous ground plane. There should also
be a 4.7 F or larger value bypass capacitor for each main sup-
ply—AVDD, RGVDD, HVDD, and DRVDD—although this
is not necessary for each individual pin. In most applications,
it is easier to share the supply for RGVDD and HVDD, which
may be done as long as the individual supply pins are separately
bypassed. A separate 3 V supply may also be used for DRVDD,
but this supply pin should still be decoupled to the same ground
plane as the rest of the chip. A separate ground for DRVSS is not
recommended. It is recommended that the exposed paddle on
the bottom of the package be soldered to a large pad, with mul-
tiple vias connecting the pad to the ground plane.
The analog bypass pins (REFT, REFB) should also be
carefully decoupled to ground as close as possible to their
respective pins. The analog input (CCDIN) capacitor
should also be located close to the pin.
The H1–4 and RG traces should be designed to have low
inductance to avoid excessive distortion of the signals. Heavier
traces are recommended because of the large transient current
demand on H1–4 by the CCD. If possible, physically locating the
AD9991 closer to the CCD will reduce the inductance on these
lines. As always, the routing path should be as direct as possible
from the AD9991 to the CCD.
The AD9991 also contains an on-chip oscillator for driving an
external crystal. Figure 39 shows an example application using
a typical 24 MHz crystal. For the exact values of the external
resistors and capacitors, it is best to consult with the crystal
manufacturer’s data sheet.
20pF
D
1
0
35
20pF
CLI
CLO
AD9991
24MHz
XTAL
34
Figure 39. Crystal Driver Application
OUTPUT FROM CCD
10
DATA OUTPUTS
LINE/FIELD/DCLK TO ASIC/DSP
3V
ANALOG
SUPPLY
EXTERNAL SYNC FROM ASIC/DSP
3
SERIAL INTERFACE TO ASIC OR DSP
TO STROBE CIRCUIT
TO MECHANICAL SHUTTER CIRCUIT
3V
ANALOG
SUPPLY
3V
RG
SUPPLY
3V
H1–H4
SUPPLY
5
+
MASTER CLOCK INPUT
12
V1–V4,
VSG1–VSG4,
SUBCK
TO V-DRIVER
3V
DRIVER
SUPPLY
VSUB TO CCD
RG, H1–H4 TO CCD
+
TOP VIEW
AD9991
PIN 1
IDENTIFIER
42
SDI
41
SL
40
REFB
39
REFT
38
AVSS
37
CCDIN
36
AVDD
35
CLI
34
CLO
33
TCVDD
32
TCVSS
31
RGVDD
30
RG
29
RGVSS
D3
1
D4
2
D5
3
D6
4
D7
5
D8
6
D9
7
DRVDD
8
DRVSS
9
VSUB 10
SUBCK 11
V1 12
V2 13
V3 14
56
D2
55
D1
54
D0
53
NC
52
NC
51
DCLK
50
HD
49
DVDD
48
DVSS
47
VD
46
SYNC
45
STROBE
44
MSHUT
43
SCK
V4
15
V5
16
V6
17
VSG1
18
VSG2
19
VSG3
2
0
VSG4
21
VSG5
22
H1
23
H2
24
HVSS
25
HVDD
26
H3
27
H4
28
+
Figure 38. AD9991 Typical Circuit Conguration
REV. 0
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