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參數(shù)資料
| 型號： | AD9980KSTZ-95 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE 8BIT ANALOG 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 應(yīng)用： | 視頻 |
| 接口： | 模擬 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
| 配用： | AD9980/PCBZ-ND - KIT EVALUATION AD9980 |
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AD9980
Rev. 0 | Page 35 of 44
0x1F
2:1
Output Drive Strength
These two bits select the drive strength for all high-
speed digital outputs (except VSOUT, A0, and the O/E
field). Higher drive strength results in faster rise/fall
times and in general makes it easier to capture data.
Lower drive strength results in slower rise/fall times
and helps reduce EMI and digitally generated power
supply noise. The power-up default setting is 10.
Table 52. Output Drive Strength
Output
Drive
Result
00
Low output drive strength
01
Medium low output drive strength
10
Medium high output drive strength
11
High output drive strength
0x1F
0
Output Clock Invert
This bit allows inversion of the output clock. The
power-up default setting is 0.
Table 53. Output Clock Invert
Select
Result
0
Noninverted pixel clock
1
Inverted pixel clock
0x20
7:6
Output Clock Select
These bits allow selection of optional output clocks
such as a fixed 40 MHz clock, a 2× clock, a 90° phase-
shifted clock or the normal pixel clock. The power-up
default setting is 00.
Table 54. Output Clock Select
Select
Result
00
Pixel clock
01
90° phase-shifted pixel clock
10
2× pixel clock
11
40 MHz internal clock
0x20
5
Output High Impedance
This bit puts all outputs (except SOGOUT) in a high impedance
state. The power-up default setting is 0.
Table 55. Output High Impedance
Select
Result
0
Normal outputs
1
All outputs (except SOGOUT) in high impedance mode
0x20
4
SOG High Impedance
This bit allows the SOGOUT pin to be placed in high
impedance mode. The power-up default setting is 0.
Table 56. SOGOUT High Impedance
Select
Result
0
Normal SOG output
1
SOGOUT pin is in high impedance mode
0x20
3
Field Output Polarity
This bit sets the polarity of the field output bit. The
power-up default setting is 1.
Table 57. Field Output Polarity
Select
Result
0
Active low = even field; active high = odd field
1
Active low = odd field; active high = even field
SYNC PROCESSING
0x20
2
PLL Sync Filter
This bit selects which signal the PLL uses. It can select
between either raw Hsync or SOG or filtered versions.
The filtering of the Hsync and SOG can eliminate
nearly all extraneous transitions which have tradi-
tionally caused PLL disruption. The power-up default
setting is 0.
Table 58. PLL Sync Filter Enable
Select
Result
0
PLL uses raw Hsync or SOG inputs
1
PLL uses filtered Hsync or SOG inputs
0x20
1
Sync Processing Input Source
This bit selects whether the sync processor uses a raw
sync or a regenerated sync for the following functions:
Coast, H/V count, field detection and Vsync duration
counts. Using the regenerated sync is recommended.
Table 59. SP Filter Enable
Select
Result
0
Sync processing uses raw Hsync or SOG
1
Sync processing uses the internally regenerated
Hsync
0x20
0
Must be set to 1 for proper operation
0x21
7:0
Must be set to default
0x22
7:0
Must be set to default
0x23
7:0
Sync Filter Window Width
This 8-bit register sets the window of time for the regenerated
Hsync leading edge (in 25 ns steps) when sync pulses are
allowed to pass through. Therefore with the default value of 10,
the window width is ±250 ns. The goal is to set the window
width so that extraneous pulses are rejected. (see the Sync
Processing section). As in the sync separator threshold, the
25 ns multiplier value is somewhat variable. The maximum
variability over all operating conditions is ±20% (20 ns to
30 ns).
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