參數(shù)資料
型號(hào)： AD9980KSTZ-95
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 26/44頁(yè)
文件大?。?/td> 0K
描述： IC INTERFACE 8BIT ANALOG 80LQFP
標(biāo)準(zhǔn)包裝： 90
應(yīng)用： 視頻
接口： 模擬
電源電壓： 3.13 V ~ 3.47 V
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 管件
安裝類型： 表面貼裝
配用： AD9980/PCBZ-ND - KIT EVALUATION AD9980
AD9980
Preliminary Technical Data
Rev. 0 | Page 32 of 44
0x18
4
Clamp Source
This bit determines the source of clamp timing. A 0
enables the clamp timing circuitry controlled by
clamp placement and clamp duration. The clamp posi-
tion and duration is counted from the leading edge of
Hsync. A 1 enables the external clamp input pin. The
three channels are clamped when the clamp signal is
active. The polarity of clamp is determined by the
clamp polarity bit. The power-up default setting
is 0.
Table 31. Clamp Source Selection Settings
Clamp Source
Result
0
Internally generated clamp
1
Externally provided clamp signal
0x18
3
Red Clamp Select
This bit determines whether the red channel is
clamped to ground or to midscale. The power-up
default setting is 0.
Table 32. Red Clamp Select Settings
Clamp
Result
0
Clamp to ground
1
Clamp to midscale
0x18
2
Green Clamp Select
This bit determines whether the green channel is
clamped to ground or to midscale. The power-up
default setting is 0.
Table 33. Green Clamp Select Settings
Clamp
Result
0
Clamp to ground
1
Clamp to midscale
0x18
1
Blue Clamp Select
This bit determines whether the blue channel is
clamped to ground or to midscale. The power-up
default setting is 0.
Table 34. Blue Clamp Select Settings
Clamp
Result
0
Clamp to ground
1
Clamp to midscale
0x19
7:0
Clamp Placement
An 8-bit register that sets the position of the internally
generated clamp.
When EXTCLMP = 0 (Register 0x18, Bit 4), a clamp
signal is generated internally at a position established
by the clamp placement register (0x19) and for a
duration set by the clamp duration register (0x1A).
Clamping starts a clamp placement (Register 0x19)
count of pixel periods after the trailing edge of Hsync.
The clamp placement may be programmed to
any value between 1 and 255. A value of 0 is
not supported.
The clamp should be placed during a time that the
input signal presents a stable black-level reference,
usually the back porch period between Hsync and the
image. When EXTCLMP = 1, this register is ignored.
Power-up default setting is 8.
0x1A
7:0
Clamp Duration
An 8-bit register that sets the duration of the
internally generated clamp.
When EXTCLMP = 0 (Register 0x18, Bit 4), a clamp
signal is generated internally at a position established
by the clamp placement register and for a duration set
by the clamp duration register. Clamping begins a
clamp placement (Register 0x19) count of pixel peri-
ods after the trailing edge of Hsync. The clamp dura-
tion may be programmed to any value between 1 and
255. A value of 0 is not supported.
For the best results, the clamp duration should be set
to include the majority of the black reference signal
time that follows the Hsync signal trailing edge.
Insufficient clamping time can produce brightness
changes at the top of the screen, and a slow recovery
from large changes in the average picture level (APL),
or brightness. When EXTCLMP = 1, this register is
ignored. Power-up default setting is 20 DDR.
0x1B
7
Clamp Polarity Override
This bit is used to override the internal circuitry that
determines the polarity of the clamp signal. The
power-up default setting is 0.
Table 35. Clamp Polarity Override Settings
Override Bit
Result
0
Clamp polarity determined by chip
1
Clamp polarity determined by user
Register 0x1B, Bit 6
0x1B
6
Input Clamp Polarity
This bit indicates the polarity of the clamp signal only
if Bit 7 of Register 0x1B = 1. The power-up default
setting is 1.
Table 36. Clamp Polarity Override Settings
CLMPOL
Result
0
Active low
1
Active high
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