參數(shù)資料
型號： AD9980KSTZ-95
廠商： Analog Devices Inc
文件頁數(shù)： 21/44頁
文件大?。?/td> 0K
描述： IC INTERFACE 8BIT ANALOG 80LQFP
標準包裝： 90
應用： 視頻
接口： 模擬
電源電壓： 3.13 V ~ 3.47 V
封裝/外殼： 80-LQFP
供應商設備封裝： 80-LQFP（14x14）
包裝： 管件
安裝類型： 表面貼裝
配用： AD9980/PCBZ-ND - KIT EVALUATION AD9980
AD9980
Preliminary Technical Data
Rev. 0 | Page 28 of 44
DETAILED 2-WIRE SERIAL CONTROL REGISTER DESCRIPTIONS
CHIP IDENTIFICATION
0x00
7:0
Chip Revision
An 8-bit register which represents the silicon revision.
PLL DIVIDER CONTROL
0x01
7:0
PLL Divide Ratio MSBs
The eight MSBs of the 12-bit PLL divide ratio PLLDIV.
The PLL derives a pixel clock from the incoming
Hsync signal. The pixel clock frequency is then
divided by an integer value, such that the output is
phase-locked to Hsync. This PLLDIV value
determines the number of pixel times (pixels plus
horizontal blanking overhead) per line. This is
typically 20% to 30% more than the number of active
pixels in the display.
The 12-bit value of the PLL divider supports divide
ratios from 2 to 4095 as long as the output frequency
is within range. The higher the value loaded in this
register, the higher the resulting clock frequency with
respect to a fixed Hsync frequency.
VESA has established some standard timing
specifications, which will assist in determining the
value for PLLDIV as a function of horizontal and
vertical display resolution and frame rate (see Table 9).
However, many computer systems do not conform
precisely to the recommendations and these numbers
should be used only as a guide. The display system
manufacturer should provide automatic or manual
means for optimizing PLLDIV. An incorrectly set
PLLDIV usually produces one or more vertical noise
bars on the display. The greater the error, the greater
the number of bars produced.
The power-up default value of PLLDIV is 1693.
PLLDIVM = 0x69, PLLDIVL = 0xDx.
The AD9980 updates the full divide ratio only when
the LSBs are written. Writing to this register by itself
does not trigger an update.
0x02
7:4
PLL Divide Ratio LSBs
The four LSBs of the 12-bit PLL divide ratio PLLDIV.
The power-up default value of PLLDIV is 1693.
PLLDIVM = 0x69, PLLDIVL = 0xDx.
CLOCK GENERATOR CONTROL
0x03
7:6
VCO Range Select
Two bits that establish the operating range of the clock
generator. VCORNGE must be set to correspond to
the desired operating frequency (incoming pixel rate).
The PLL gives the best jitter performance at high
frequencies. For this reason, in order to output low
pixel rates and still get good jitter performance, the
PLL actually operates at a higher frequency but then
divides down the clock rate afterwards. See Table 13
for the pixel rates for each VCO range setting. The
PLL output divisor is automatically selected with the
VCO range setting. The power-up default value is 01.
Table 13. VCO Ranges
VCO Range
Pixel Rates
00
10 to 21
01
21 to 42
10
42 to 84
11
84 to 95
0x03
5:3
Charge Pump Current
Three bits that establish the current driving the loop
filter in the clock generator. The current must be set to
correspond with the desired operating frequency. The
power-up default value is current = 001.
Table 14. Charge Pump Currents
Ip2
Ip1
Ip0
Current
0
50
0
1
100
0
1
0
150
0
1
250
1
0
350
1
0
1
500
1
0
750
1
1500
0x03
2
External Clock Enable
This bit determines the source of the pixel clock.
Table 15. External Clock Select Settings
EXTCLK
Function
0
Internally generated clock
1
Externally provided clock signal
A Logic 0 enables the internal PLL that generates the
pixel clock from an externally provided Hsync.
A Logic 1 enables the external EXTCLK input pin. In
this mode, the PLL Divide Ratio (PLLDIV) is ignored.
The clock phase adjust (PHASE) is still functional.
The power-up default value is EXTCLK = 0.
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