參數(shù)資料
型號: AD9980KSTZ-95
廠商: Analog Devices Inc
文件頁數(shù): 20/44頁
文件大小: 0K
描述: IC INTERFACE 8BIT ANALOG 80LQFP
標(biāo)準(zhǔn)包裝: 90
應(yīng)用: 視頻
接口: 模擬
電源電壓: 3.13 V ~ 3.47 V
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(14x14)
包裝: 管件
安裝類型: 表面貼裝
配用: AD9980/PCBZ-ND - KIT EVALUATION AD9980
AD9980
Rev. 0 | Page 27 of 44
Hexadecimal
Address
Read and
Write or
Read Only
Bits
Default
Value
Register
Name
Description
0x26
RO
7:0
Hsyncs Per
Vsync MSBs
MSBs of Hsyncs per Vsync count.
0x27
RO
7:4
Hsyncs Per
Vsync LSBs
LSBs of Hsyncs per Vsync count.
0x28
R/W
7:0
1011 1111
TestReg1
Must be written to 0xBF for proper operation.
0x29
R/W
7:0
0000 0010
TestReg2
Must be written to 0x02 for proper operation.
0x2A
RO
7:0
TestReg3
Read-only bits for future use.
0x2B
RO
7:0
TestReg4
Read-only bits for future use.
0x2C
R/W
7:5
000* ****
Offset Hold
Must be written to default for proper operation.
4
***0 ****
Auto-Offset Hold.
Disables the auto-offset and holds the feedback result.
1 = One time update.
0 = Continuous update.
3:0
**** 0000
Must be written to default for proper operation.
0x2D
R/W
7:0
1111 0000
TestReg5
Must be written to 0xE8 for proper operation.
0x2E
R/W
7:0
1111 0000
TestReg6
Must be written to 0xE0 for proper operation.
1 Functions with more than eight control bits, such as PLL divide ratio, gain, and offset, are only updated when the LSBs are written to (for example, Register 0x02 for
PLL divide ratio).
2 Gain registers (Register 0x05, Register 0x07 and Register 0x09) when written to must each be followed with a write to their next register: Register 0x05 and Register
0x06, Register 0x07 and Register 0x08, and Register 0x09 and Register 0x0A.
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