參數(shù)資料
型號(hào)： AD9959BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/44頁(yè)
文件大?。?/td> 0K
描述： IC DDS QUAD 10BIT DAC 56LFCSP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝： 750
分辨率（位）： 10 b
主 fclk： 500MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.71 V ~ 1.96 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 帶卷 (TR)
AD9959
Rev. B | Page 13 of 44
–170
–160
–150
–140
–130
–120
–110
–100
10
100
1k
10k
100k
1M
10M
FREQUENCY OFFSET (Hz)
PH
A
S
E
N
O
ISE
(
d
B
c/
H
z)
05
246
-03
4
75.1MHz
100.3MHz
40.1MHz
15.1MHz
Figure 16. Residual Phase Noise (SSB) with fOUT = 15.1 MHz, 40.1 MHz,
75.1 MHz, 100.3 MHz; fCLK = 500 MHz with REFCLK Multiplier Bypassed
–70
–170
10
10M
05
24
6-
0
35
FREQUENCY OFFSET (Hz)
PH
A
S
E
N
O
ISE
(
d
B
c/
H
z)
–80
–90
–100
–110
–120
–130
–140
–150
–160
100
1k
10k
100k
1M
100.3MHz
75.1MHz
15.1MHz
40.1MHz
Figure 17. Residual Phase Noise (SSB) with fOUT = 15.1 MHz, 40.1 MHz,
75.1 MHz, 100.3 MHz; fCLK = 500 MHz with REFCLK Multiplier = 5×
–70
–170
10
10M
05
24
6-
0
36
FREQUENCY OFFSET (Hz)
P
HAS
E
NO
IS
E
(
d
Bc/
H
z)
–80
–90
–100
–110
–120
–130
–140
–150
–160
100
1k
10k
100k
1M
100.3MHz
75.1MHz
15.1MHz
40.1MHz
Figure 18. Residual Phase Noise (SSB) with fOUT = 15.1 MHz, 40.1 MHz,
75.1 MHz,100.3 MHz; fCLK = 500 MHz with REFCLK Multiplier = 20×
–60
–85
25.3
200.3
05
24
6-
0
37
FREQUENCY OF COUPLING SPUR (MHz)
CHANN
E
L
I
S
O
L
A
T
IO
N
(
d
Bc)
–65
–70
–75
–80
50.3
75.3
100.3
125.3
150.3
175.3
SEPARATE DAC POWER PLANES
SINGLE DAC POWER PLANE
Figure 19. Channel Isolation at 500 MSPS Operation; Conditions are Channel
of Interest Fixed at 110.3 MHz, the Other Channels Are Frequency Swept
600
0
500
05
24
6-
0
38
REFERENCE CLOCK FREQUENCY (MHz)
TO
TA
L
P
O
W
E
R
D
IS
S
IP
A
T
IO
N
(
m
W
) 500
400
300
200
100
450
400
350
300
250
200
150
100
50
3 CHANNELS ON
4 CHANNELS ON
2 CHANNELS ON
1 CHANNEL ON
Figure 20. Power Dissipation vs. Reference Clock Frequency vs. Channel(s)
Power On/Off
–45
–75
1.1
05
24
6-
04
5
fOUT (MHz)
S
F
DR
(
d
B
c)
–50
–55
–60
–65
–70
15.1
40.1
75.1
100.3
200.3
SFDR AVERAGED
Figure 21. Averaged Channel SFDR vs. fOUT
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