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| 型號： | AD9959BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/44頁 |
| 文件大小： | 0K |
| 描述： | IC DDS QUAD 10BIT DAC 56LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計資源： | Phase Coherent FSK Modulator (CN0186) |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 500MHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.71 V ~ 1.96 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9959
Rev. B | Page 36 of 44
REGISTER MAPS AND BIT DESCRIPTIONS
REGISTER MAPS
Table 28. Control Register Map
Register
Name
(Serial
Address)
Bit
Range
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
Channel
Select
Register
(CSR)
(0x00)
[7:0]
Channel 2
Channel 1
Channel 0
Must
be 0
Serial I/O mode
select[2:1]
LSB first
0xF0
Function
Register 1
(FR1)
(0x01)
[23:16]
VCO gain
control
PLL divider ratio[22:18]
Charge pump
control[17:16]
0x00
[15:8]
Open
Profile pin configuration (PPC)[14:12]
Ramp-up/
ramp-down
(RU/RD)[11:10]
Modulation level[9:8]
0x00
[7:0]
Reference
clock input
power-down
External power-
down mode
SYNC_CLK
disable
DAC reference
power-down
Open[3:2]
Manual
hardware
sync
Manual
software
sync
0x00
Function
Register 2
(FR2)
(0x02)
[15:8]
All channels
autoclear
sweep
accumulator
All channels
clear sweep
accumulator
All channels
autoclear phase
accumulator
All channels
clear phase
accumulator
Open[11:10]
Open[9:8]
0x00
[7:0]
Auto sync
enable
Multidevice sync
master enable
Multidevice sync
status
Multidevice sync
mask
Open[3:2]
System clock
offset[1:0]
0x00
1 Channel enable bits do not require an I/O update to be activated. These bits are active immediately after the byte containing the bits is written. All other bits need an
I/O update to become active. The four channel enable bits shown in Table 28 are used to enable/disable any combination of the four channels. The default for all four
channels is enabled.
In the channel select register, if the user wants four different
frequencies for all four DDS channels, use the following
protocol:
1.
Enable (Logic 1) the Channel 0 enable bit, which is located
in the channel select register, and disable the other three
channels (Logic 0).
2.
Write the desired frequency tuning word for Channel 0, as
described in Step 1, and then disable the Channel 0 enable
bit (Logic 0).
3.
Enable the Channel 1 enable bit only, located in the
channel select register, and disable the other three
channels.
4.
Write the desired frequency tuning word for Channel 1 in
Step 3, then disable the Channel 1 enable bit.
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