- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1894 > AD9959BCPZ-REEL7 (Analog Devices Inc)IC DDS QUAD 10BIT DAC 56LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9959BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 36/44頁 |
| 文件大小： | 0K |
| 描述： | IC DDS QUAD 10BIT DAC 56LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計資源： | Phase Coherent FSK Modulator (CN0186) |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 500MHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.71 V ~ 1.96 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當(dāng)前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
AD9959
Rev. B | Page 41 of 44
DESCRIPTIONS FOR CHANNEL REGISTERS
Channel Function Register (CFR)—Address 0x03
Three bytes are assigned to this register.
Table 34. Bit Descriptions for CFR
Bit
Mnemonic
Description
23:22
Amplitude frequency
phase (AFP) select
Controls what type of modulation is to be performed for that channel. See the Modulation Mode section
for details.
21:16
Open
15
Linear sweep no-dwell
0 = the linear sweep no-dwell function is inactive (default).
1 = the linear sweep no-dwell function is active. If CFR[15] is active, the linear sweep no-dwell function is
activated. See the Linear Sweep Mode section for details. If CFR[14] is clear, this bit is don’t care.
14
Linear sweep enable
0 = the linear sweep capability is inactive (default).
1 = the linear sweep capability is enabled. When enabled, the delta frequency tuning word is applied to
the frequency accumulator at the programmed ramp rate.
13
Load SRR at
I/O_UPDATE
0 = the linear sweep ramp rate timer is loaded only upon timeout (timer = 1) and is not loaded because
of an I/O_UPDATE input signal (default).
1 = the linear sweep ramp rate timer is loaded upon timeout (timer = 1) or at the time of an I/O_UPDATE
input signal.
12:11
Open
10
Must be 0
Must be set to 0.
9:8
DAC full-scale current
control
11 = the DAC is at the largest LSB value (default).
See Table 5 for other settings.
7
Digital power-down
0 = the digital core is enabled for operation (default).
1 = the digital core is disabled and is in its lowest power dissipation state.
6
DAC power-down
0 = the DAC is enabled for operation (default).
1 = the DAC is disabled and is in its lowest power dissipation state.
5
Matched pipe delays
0 = matched pipe delay mode is inactive (default).
active
1 = matched pipe delay mode is active. See the Single-Tone Mode—Matched Pipeline Delay section for
details.
4
Autoclear sweep
accumulator
0 =
the current state of the sweep accumulator is not impacted by receipt of an I/O_UPDATE signal
(default).
1 = t
he sweep accumulator is automatically and synchronously cleared for one cycle upon receipt
of an I/O_UPDATE signal.
3
Clear sweep
0 = the sweep accumulator functions as normal (default).
accumulator
1 = the sweep accumulator memory elements are asynchronously cleared.
2
Autoclear phase
accumulator
0 = t
he current state of the phase accumulator is not impacted by receipt of an I/O_UPDATE signal
(default).
1 = t
he phase accumulator is automatically and synchronously cleared for one cycle upon receipt
of an I/O_UPDATE signal.
1
Clear phase
0 = the phase accumulator functions as normal (default).
accumulator
1 = the phase accumulator memory elements are asynchronously cleared.
0
Sine wave output
0 = the angle-to-amplitude conversion logic employs a cosine function (default).
enable
1 = the angle-to-amplitude conversion logic employs a sine function.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9970BCPZRL7 | IC PROCESSOR CCD SIGNAL 32-LFCSP |
| AD9972BBCZRL | IC CCD SGNL PROC 14BIT 100CSPBGA |
| AD9973BBCZ | IC CCD SGNL PROC 14BIT 84-CSPBGA |
| AD9974BBCZRL | IC CCDSP DUAL 14BIT 100-CSPBGA |
| AD9979BCPZRL | IC PROCESSOR CCD 14BIT 48-LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9959BCPZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
| AD995PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| AD9960BSTZ | 功能描述:RFID應(yīng)答器 MxFE for RFID Reader Transceiver RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| AD9960BSTZRL | 功能描述:IC MXFE FOR RFID READER/TXRX RoHS:是 類別:RF/IF 和 RFID >> RFID IC 系列:AD9960B 其它有關(guān)文件:CR14 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- RF 型:收發(fā)器 頻率:13.56MHz 特點(diǎn):ISO14443-B 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SO 包裝:Digi-Reel® 其它名稱:497-5719-6 |
| AD9960XSTZ | 制造商:Analog Devices 功能描述:SINGLE-SUPPLY CABLE MODEM/SET-TOP BOX MIXED-SIGNAL FRONT END - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。