V
參數(shù)資料
型號(hào)： AD9959BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 42/44頁
文件大?。?/td> 0K
描述： IC DDS QUAD 10BIT DAC 56LFCSP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝： 750
分辨率（位）： 10 b
主 fclk： 500MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.71 V ~ 1.96 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 帶卷 (TR)
AD9959
Rev. B | Page 7 of 44
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CMOS LOGIC OUTPUTS
1 mA load
VOH
2.7
V
VOL
0.4
V
POWER SUPPLY
Total Power Dissipation—All Channels On,
Single-Tone Mode
540
635
mW
Dominated by supply variation
Total Power Dissipation—All Channels On,
with Sweep Accumulator
580
680
mW
Dominated by supply variation
Total Power Dissipation—Full Power-Down
13
mW
IAVDD—All Channels On, Single-Tone Mode
155
180
mA
IAVDD—All Channels On, Sweep Accumulator, REFCLK
Multiplier and 10-Bit Output Scalar Enabled
160
185
mA
IDVDD—All Channels On, Single-Tone Mode
105
125
mA
IDVDD—All Channels On, Sweep Accumulator, REFCLK
Multiplier and 10-Bit Output Scalar Enabled
125
145
mA
IDVDD_I/O
40
mA
IDVDD = read
30
mA
IDVDD = write
IAVDD Power-Down Mode
0.7
mA
IDVDD Power-Down Mode
1.1
mA
DATA LATENCY (PIPELINE DELAY) SINGLE-TONE MODE2,3
Frequency, Phase, and Amplitude Words to DAC
Output with Matched Latency Enabled
29
SYSCLK
s
Frequency Word to DAC Output with Matched
Latency Disabled
29
SYSCLK
s
Phase Offset Word to DAC Output with Matched
Latency Disabled
25
SYSCLK
s
Amplitude Word to DAC Output with Matched
Latency Disabled
17
SYSCLK
s
DATA LATENCY (PIPELINE DELAY) MODULATION MODE3,4
Frequency Word to DAC Output
34
SYSCLK
s
Phase Offset Word to DAC Output
29
SYSCLK
s
Amplitude Word to DAC Output
21
SYSCLK
s
DATA LATENCY (PIPELINE DELAY) LINEAR SWEEP MODE3,4
Frequency Rising/Falling Delta Tuning Word to DAC
Output
41
SYSCLK
s
Phase Offset Rising/Falling Delta Tuning Word to
DAC Output
37
SYSCLK
s
Amplitude Rising/Falling Delta Tuning Word to DAC
Output
29
SYSCLK
s
1 For the VCO frequency range of 160 MHz to 255 MHz, there is no guarantee of operation.
2 Data latency is referenced to I/O_UPDATE.
3 Data latency is fixed.
4 Data latency is referenced to a profile change.
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