參數(shù)資料
型號(hào)： AD9959BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/44頁(yè)
文件大小： 0K
描述： IC DDS QUAD 10BIT DAC 56LFCSP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝： 750
分辨率（位）： 10 b
主 fclk： 500MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.71 V ~ 1.96 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 帶卷 (TR)
AD9959
Rev. B | Page 30 of 44
I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK
RELATIONSHIPS
I/O_UPDATE and SYNC_CLK are used together to transfer
data from the serial I/O buffer to the active registers in the
device. Data in the buffer is inactive.
SYNC_CLK is a rising edge active signal. It is derived from
the system clock and a divide-by-4 frequency divider. The
SYNC_CLK, which is externally provided, can be used to
synchronize external hardware to the AD9959 internal clocks.
I/O_UPDATE initiates the start of a buffer transfer. It can be
sent synchronously or asynchronously relative to the SYNC_CLK.
If the setup time between these signals is met, then constant
latency (pipeline) to the DAC output exists. For example, if
repetitive changes to phase offset via the SPI port is desired, the
latency of those changes to the DAC output is constant; otherwise,
a time uncertainty of one SYNC_CLK period is present.
The I/O_UPDATE is essentially oversampled by the SYNC_CLK.
Therefore, I/O_UPDATE must have a minimum pulse width
greater than one SYNC_CLK period.
The timing diagram shown in Figure 40 depicts when data in
the buffer is transferred to the active registers.
SYNC_CLK
SYSCLK
AB
NN + 1
N – 1
DATA IN
REGISTERS
DATA IN
I/O BUFFERS
N
N + 1
N + 2
I/O_UPDATE
THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B. 05
24
6-
04
9
Figure 40. I/O_UPDATE Transferring Data from I/O Buffer to Active Registers
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