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參數(shù)資料
| 型號： | AD9929 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Precision Timing Generator |
| 中文描述： | CCD信號處理器精確時序發(fā)生器 |
| 文件頁數(shù)： | 49/64頁 |
| 文件大?。?/td> | 558K |
| 代理商： | AD9929 |
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AD9929
Rev. A | Page 49 of 64
VD
XVSGLEN_0
XVSGACTLINE
HD
NOTES
1. XVSGTOG_x (x = 0, 1) REFERENCES THE 13-BIT ST COUNTER
2. XVSGACTLINE (PROGRAMMABLE AT MODE_REG(1))
3. XVSGLEN (PROGRAMMABLE AT SYS_REG(14))
PROGRAMMABLE CLOCK POSITIONS
1. XVSGTOG_0 (PROGRAMMABLE AT SYS_REG(13))
2. XVSGTOG_1 (PROGRAMMABLE AT SYS_REG(13))
1
13-BIT
ST COUNTER
(FIXED)
0
1
2
3
XVSGTOG_0
XVSGLEN_1
0
2
XVSGTOG_1
Figure 55. Example of VSG Pulse
VD
HD
VSUB
1
2
3
4
5
6
SERIAL
WRITES
2 LINES
3 LINES
0
Figure 56. VSUB Timing Example
VSUB TIMING
The CCD readout bias (VSUB) can be programmed to accom-
modate different CCDs. VSUB on and off toggle positions and
polarity are controlled using VSUBTOG (Address 0x0D) and
VSUBPOL (Address 0x0D) registers, respectively, as described
in Table 36. Since the VSUBTOG is an 11-bit register, the VSUB
on position is programmable within any line. Figure 56 shows
an example of controlling VSUB using these registers.
Table 36. VSUB Registers
Register
Name
Width
Type
VSUBPOL
1
Control
Bit
Register
Range
(Lines)
–
Description
(0 = Low,
1 = High)
VSUB toggle
position
VSUBTOG
11
Control
0–2048
VSUB Placement and Polarity
Figure 56 shows the sequence of events for programming the
VSUB on and off toggle positions and polarity.
1.
2.
Program VSUBTOG = 2 and VSUBPOL = 1.
Since the VSUBTOG and VSUBPOL are VD synchronous
type registers, the falling edge of VD updates the serial
writes from Step 1.
VSUB is asserted high after two HD cycles.
3.
4.
5.
Program VSUBTOG = 3 and VSUBPOL = 0.
Since the VSUBTOG and VSUBPOL are VD synchronous
type registers, the falling edge of VD updates the serial
writes from Step 4.
VSUB is asserted low after three HD cycles.
6.
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