參數(shù)資料
型號： AD9929
廠商： Analog Devices, Inc.
英文描述： CCD Signal Processor with Precision Timing Generator
中文描述： CCD信號處理器精確時序發(fā)生器
文件頁數(shù)： 27/64頁
文件大?。?/td> 558K
代理商： AD9929
AD9929
EXTERNAL SYNCHRONIZATION (MASTER MODE)
External synchronization can be applied to synchronize the VD
and HD signals by applying an external pulse on the
SYNC/GATE (Pin 45) pin for master mode operation. The
SYNC/GATE pin is configured as an external SYNC input for
master mode operation by setting the SLAVE_MODE register
(Address 0xD6) = 0 (the AD9929 defaults to slave mode at
power-up).
Rev. A | Page 27 of 64
SYNCCNT (Address 0x0A) and SYNCPOL (Address 0x01) are
the only two registers used for configuring the AD9929 for
external synchronization. The SYNCPOL is a 1-bit register used
for configuring the SYNC input as either active low or active
high. The AD9929 defaults to active low at power-up. The
function of the SYNCCNT register is described in Table 17.
Figure 20 and Figure 21 provide two examples of external
synchronization with SYNCPOL = 0.
Table 17. External Synchronization (Master Mode)
SYNCCNT
External Synchronization Options
0
Disable External Synchronization
1
VD Sync at every SYNC Pulse
2
VD Sync after 2nd Applied SYNC Pulse
3
VD Sync after 3rd Applied SYNC Pulse
4
VD Sync after 4th Applied SYNC Pulse
5
VD Sync after 5th Applied SYNC Pulse
6
VD Sync after 6th Applied SYNC Pulse
7
VD Sync after 7th Applied SYNC Pulse
8
VD Sync after 8th Applied SYNC Pulse
9
VD Sync after 9th Applied SYNC Pulse
10
VD Sync after 10th Applied SYNC Pulse
11
VD Sync after 11th Applied SYNC Pulse
12
VD Sync after 12th Applied SYNC Pulse
13
VD Sync after 13th Applied SYNC Pulse
14
VD Sync after 14th Applied SYNC Pulse
15
VD Sync after 1st Applied SYNC Pulse Only
VD
SYNC
4 CLI
2 CLI
MIN
4 CLI
4 CLI
MODE A
MODE B
SERIAL
WRITES
CHANGE TO MODE B
OPERATION
MODE
0
Figure 20. Example of Synchronization with SYNCPOL = 0 and SYNCCNT = 1
VD
SYNC
4 CLI
2 CLI
MIN
4 CLI
4 CLI
0
Figure 21. Example of Synchronization with SYNCPOL = 0 and CYNCCNT = 3
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