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| 型號： | AD9929 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Precision Timing Generator |
| 中文描述： | CCD信號處理器精確時序發(fā)生器 |
| 文件頁數(shù)： | 31/64頁 |
| 文件大?。?/td> | 558K |
| 代理商： | AD9929 |
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AD9929
H1 AND H2 BLANKING
The AD9929 provides three options for controlling the period
where H1 and H2 pulses get blanked. These options are normal
H blanking, selective positioning for 2 H1 and H2 outputs, and
extended blanking. In all cases, HBLKMASK is used to set the
polarity of H1 during the blanking period. Table 21 describes
the registers used to control H blanking.
Normal H-Blanking
For normal H-blanking operation, HPULSECNT = 0 and
BLKMASK = 0 or 1. The HBLKPOS register isn’t used in this
mode. Figure 27 shows one example where HBLKMASK = 0
and H1 and H2 are blanked while HD is low.
Table 21. H1 Blanking Registers
Register
Name
Width
Control (0x01)
Rev. A | Page 31 of 64
Selective Positioning for Two H1 and H2 Outputs
For selective positioning operation, HPULSECNT = 1 and
HBLKMASK = 0 or 1. In this mode, two H1 pulses are output
during the blanking period. The location of these two pulse is
set using the HBLKPOS register, as shown in Figure 28.
Extended Blanking
Extended blanking is enabled by setting HBLKEXT = 1. The
HBLKEXT register uses the 9-bit BL counter to suspend
operation of the HD and HL counters. This delays the blanking
period by the length set in the BLLEN register, as shown in
Figure 29.
Bit
Register Type
Description
HBLKMASK
1
Masking Polarity for H1 during Blanking Period
1
(0 = Low, 1 = High)
H Pulse Control during Blanking Period
(0 = No Output during Blanking,1 = Output during Blanking ) H Pulse Blanking Extends
Control
2
(0 = Extended Blanking Disabled, 1 = Extended Blanking Enabled)
Retimes the H1 HBLK to Internal Clock
(0 = Retiming Disabled, 1 = Retiming Enabled)
H1 Pulse ON Position during Blanking Period
HPULSECNT
1
Control (0x0A)
Control (0x0A)
HBLKEXT
1
H1BLKRETIME
1
Control (0x03)
HBLKHPOS
10
Sys_Reg(11)
1
H2 is always the opposite polarity of H1.
2
The HBLKEXT extend control extends the blanking period by the number of counts set in the BLLEN register for the 9-bit BL counter.
HD
HBLK
(INTERNAL)
RG
H1
H2
HDRISE
1
NOTES
1. THE RISING EDGE OF HBLK IS ALWAYS THE SAME AS HDRISE
0
Figure 27. Normal H-Blanking Operation HBLKMASK = 0, HPULSECNT = 0, HBLKHPOS = XXX
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