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參數(shù)資料
| 型號(hào)： | AD9929 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Precision Timing Generator |
| 中文描述： | CCD信號(hào)處理器精確時(shí)序發(fā)生器 |
| 文件頁(yè)數(shù)： | 42/64頁(yè) |
| 文件大?。?/td> | 558K |
| 代理商： | AD9929 |
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AD9929
Rev. A | Page 42 of 64
VD
HD
NOTES
1. THE XVxSPAT_TOG1 AND XVxSPAT_TOG2 REGISTERS REFERENCE THE 13-BIT ST COUNTER.
2. THE INTERNAL SPAT TIMING IS APPLIED IN THE SAME LINE AS THE XVSGx PULSE.
PROGRAMMABLE CLOCK POSITIONS
1. XVXSPAT_TOG1 (PROGRAMMABLE AT CONTROL REGS)
3. XVXSPAT_TOG3 (PROGRAMMABLE AT MODE_REGS)
2. XVXSPAT_TOG2 (PROGRAMMABLE AT CONTROL REGS)
4. XVXSPAT_TOG4 (PROGRAMMABLE AT MODE_REGS)
XVSGx
13-BIT
ST COUNTER
(FIXED)
INTERNAL SPAT
TIMING FOR XV2 WITH
SPATLOGIC = 1
1
2
XV2 OUTPUT WITH
SPAT APPLIED
INTERNAL XV2 WITHOUT
SPAT APPLIED
3
4
500
540
600
640
VSG LINE
0
Figure 39. SPAT Example for XV2 with XV2SPAT_TOG1 = 500, XV2SPAT_TOG2 = 540, XV2SPAT_TOG3 = 600, XV2SPAT_TOG4 = 640, and SPATLOGIC = XX1X
VD
HD
NOTES
1. THE XVxSPAT_TOG1 AND XVxSPAT_TOG2 REGISTERS REFERENCE THE 13-BIT ST COUNTER.
2. THE INTERNAL SPAT TIMING IS APPLIED IN THE SAME LINE AS THE XVSGx PULSE.
XVSGx
13-BIT
ST COUNTER
(FIXED)
INTERNAL XV1 WITHOUT
SPAT APPLIED
INTERNAL SPAT
TIMING FOR XV1 WITH
SPATLOGIC = 0
1
2
XV1 OUTPUT WITH
SPAT APPLIED
VSG LINE
3
4
500
540
600
640
PROGRAMMABLE CLOCK POSITIONS
1. XVXSPAT_TOG1 (PROGRAMMABLE AT CONTROL REGS)
3. XVXSPAT_TOG3 (PROGRAMMABLE AT MODE_REGS)
2. XVXSPAT_TOG2 (PROGRAMMABLE AT CONTROL REGS)
4. XVXSPAT_TOG4 (PROGRAMMABLE AT MODE_REGS)
0
Figure 40. SPAT (OR) Example for XV1 with XV1SPAT_TOG1 = 500, XV1SPAT_TOG2 = 540, XV1SPAT_TOG3 = 600, XV1SPAT_TOG4 = 640, and SPATLOGIC = XXX0
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