參數資料
型號: AD9923ABBCZRL
廠商: Analog Devices Inc
文件頁數: 8/84頁
文件大?。?/td> 0K
描述: IC PROCESSOR CCD 12BIT 105CSPBGA
標準包裝: 2,000
類型: CCD 信號處理器,12 位
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
電流 - 電源: 20mA
安裝類型: 表面貼裝
封裝/外殼: 105-LFBGA,CSPBGA
供應商設備封裝: 105-CSPBGA(8x8)
包裝: 帶卷 (TR)
AD9923A
Rev. A | Page 16 of 84
Table 11. Precision Timing Edge Locations
Quadrant
Edge Location (Decimal)
Register Value (Decimal)
Register Value (Binary)
I
0 to 11
000000 to 001011
II
12 to 23
16 to 27
010000 to 011011
III
24 to 35
32 to 43
100000 to 101011
IV
36 to 47
48 to 59
110000 to 111011
P[0]
P[48] = P[0]
P[12]
P[24]
P[36]
1 PIXEL
PERIOD
CLI
tCLIDLY
POSITION
NOTES
1. THE PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCK.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITION (tCLIDLY = 6ns TYP).
05
58
6-
01
6
Figure 17. High Speed Clock Resolution from CLI Master Clock Input
H1
H2
CCD
SIGNAL
RG
PROGRAMMABLE CLOCK POSITIONS:
1RG RISING EDGE.
2RG FALLING EDGE.
3SHP SAMPLE LOCATION.
4SHD SAMPLE LOCATION.
5HL RISING EDGE POSITION.
6HL FALLING EDGE POSITION.
7H1 RISING EDGE POSITION.
8H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1).
9H3 RISING EDGE POSITION.
10H3 FALLING EDGE POSITION (H4 IS INVERSE OF H3).
H3
H4
3
4
12
78
HL
56
910
05
58
6-
0
17
Figure 18. High Speed Clock Programmable Locations
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