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參數(shù)資料
| 型號： | AD9923ABBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標(biāo)準包裝： | 2,000 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 20mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9923A
Rev. A | Page 20 of 84
Individual HBLK Patterns
The HBLK programmable timing shown in Figure 26 is similar
to CLPOB and PBLK; however, there is no start polarity control.
Only the toggle positions are used to designate the start and end
positions of the blanking period. Additionally, there is a polarity
control register, HBLKMASK, that designates the polarity of the
horizontal clock signals during the blanking period. Setting
HBLKMASK high sets H1 = H3 = high and H2 = H4 = low
during blanking, as shown in Figure 27. As with CLPOB and
PBLK registers, HBLK registers are available in each V-sequence,
allowing different blanking signals to be used with different
vertical timing sequences.
Note that 8189 is the recommended setting for any unused
HBLK toggle locations on the AD9923A, regardless of the
setting for HBLKALT. 8190 and 8191 are not valid settings for
HBLK toggle positions that are unused and causes undesired
HBLK toggle activity.
Generating Special HBLK Patterns
There are six toggle positions available for HBLK. Normally,
only two of the toggle positions are used to generate the
standard HBLK interval. However, additional toggle positions
can be used to generate special HBLK patterns, as shown in
Figure 28. The pattern in this example uses all six toggle
positions to generate two extra groups of pulses during the
HBLK interval. By changing the toggle positions, different
patterns can be created.
Table 13. HBLK Pattern Registers
Register
Length
(Bits)
Range
Description
HBLKMASK
1
High/low
Masking polarity for H1, H3, HL (0 = mask low, 1 = mask high)
HBLKALT
3
0 to 7 alternation modes
Enables different odd/even alternation of HBLK toggle positions
0: disable alternation (HBLKTOGE1 to HBLKTOGE6 registers are used for each line)
1: TOGE1 and TOGE2 odd lines, TOGE3 to TOGE6 even lines
2: TOGE1 and TOGE2 even lines, TOGE3 to TOGE6 odd lines
3: TOGE1 to TOGE6 even lines, TOGO1 to TOGE6 odd lines (FREEZE/RESUME not
available)
4 to 7: HBLKSTART, HBLKEND, HBLKLEN, and HBLKREP registers are used for each line
HBLKTOGE1
13
0 to 8189 pixel location
HBLK first toggle position (for even lines only when HBLKALT = 3)
HBLKTOGE2
13
0 to 8189 pixel location
HBLK second toggle position (for even lines only when HBLKALT = 3)
HBLKTOGE3
13
0 to 8189 pixel location
HBLK third toggle position (for even lines only when HBLKALT = 3)
HBLKTOGE4
13
0 to 8189 pixel location
HBLK fourth toggle position (for even lines only when HBLKALT = 3)
HBLKTOGE5
13
0 to 8189 pixel location
Fifth toggle position, even lines (HBLKSTART when HBLKALT = 4 to 7)
HBLKTOGE6
13
0 to 8189 pixel location
Sixth toggle position, even lines (HBLKEND when HBLKALT = 4 to 7)
HBLKLEN
13
0 to 8189 pixels
HBLK pattern length, only used when HBLKALT = 4 to 7
HBLKREP
8
0 to 255 repetitions
Number of HBLK pattern repetitions, only used when HBLKALT = 4 to 7
HBLKTOGO1
13
0 to 8189 pixel location
First toggle position for odd lines when HBLKALT = 3 (usually VREPA_3)
HBLKTOGO2
13
0 to 8189 pixel location
Second toggle position for odd lines when HBLKALT = 3 (usually VREPA_4)
HBLKTOGO3
13
0 to 8189 pixel location
Third toggle position for odd lines when HBLKALT = 3 (usually FREEZE1)
HBLKTOGO4
13
0 to 8189 pixel location
Fourth toggle position for odd lines when HBLKALT = 3 (usually RESUME1)
HBLKTOGO5
13
0 to 8189 pixel location
Fifth toggle position for odd lines when HBLKALT = 3 (usually FREEZE2)
HBLKTOGO6
13
0 to 8189 pixel location
Sixth toggle position for odd lines when HBLKALT = 3 (usually RESUME2)
HD
HBLK
BASIC HBLK PULSE IS GENERATED USING HBLKTOGE1 AND HBLKTOGE2 REGISTERS (HBLKALT = 0).
BLANK
HBLKTOGE1
HBLKTOGE2
05
586
-02
4
Figure 26. Typical Horizontal Blanking (HBLK) Pulse Placement
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
| AD9924BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9925 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with Vertical Driver and Precision Timing Generator |
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