參數(shù)資料
型號： AD9923ABBCZRL
廠商： Analog Devices Inc
文件頁數(shù)： 51/84頁
文件大?。?/td> 0K
描述： IC PROCESSOR CCD 12BIT 105CSPBGA
標(biāo)準(zhǔn)包裝： 2,000
類型： CCD 信號處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 20mA
安裝類型： 表面貼裝
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 帶卷 (TR)
AD9923A
Rev. A | Page 55 of 84
6dB ~ 42dB
CCDIN
CLI
DIGITAL
FILTER
CLPOB
DC RESTORE
OPTICAL BLACK
CLAMP
12-BIT
ADC
VGA
DAC
8
CDS
INTERNAL
VREF
2V FULL SCALE
PRECISION
TIMING
GENERATION
SHP
SHD
1.5V
OUTPUT
DATA
LATCH
REFT
REFB
DOUT PHASE
V-H
TIMING
GENERATION
SHP SHD
DOUT
PHASE
CLPOB PBLK
PBLK
1.0V
2.0V
DOUT
DCLK
AD9923A
0.1F
VGA GAIN
REGISTER
0.1F 0.1F
CLAMP LEVEL
REGISTER
12
DOUT
DLY
DCLK
MODE
FIXED
DELAY
CLI
1
0
0
55
86
-0
71
Figure 73. Analog Front End Functional Block Diagram
ANALOG FRONT END DESCRIPTION/OPERATION
The AD9923A signal processing chain is shown in Figure 73.
Each step is essential to achieve a high quality image from the
raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc restore
circuit is used with an external 0.1 μF series coupling capacitor.
This restores the dc level of the CCD signal to approximately 1.5 V
so that it is compatible with the 3 V supply voltage of the AD9923A.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract video
information and reject low frequency noise. The timing shown in
Figure 20 illustrates how the two internally generated CDS
clocks, SHP and SHD, are used to sample the reference and data
levels of the CCD signal, respectively. The placement of the SHP
and SHD sampling edges is determined by the setting of the
SHPLOC and SHDLOC registers located at Address 0x37.
Placement of these clock signals is critical to achieve the best
CCD performance.
The CDS gain can be set to 3 dB, 0 dB (default), +3 dB, or +6 dB
in the CDSGAIN register, Address 0x04. The +3 dB and +6 dB
settings improve noise performance, but reduce the input range
(see Figure 8).
Variable Gain Amplifier
The VGA stage provides gain in the range of 6 dB to 42 dB,
programmable with 10-bit resolution through the serial digital
interface. A minimum gain of 6 dB is needed to match a 1 V input
signal with an ADC full-scale range of 2 V. When compared to 1 V
full-scale systems, the equivalent range of gain is 0 dB to 36 dB.
The VGA gain curve follows a linear-in-dB characteristic. The
exact VGA gain can be calculated for any gain register value
using the following equation
Gain (dB) = (0.0358 × Code) + 5.5 dB
where the code range is 0 to 1023.
0
55
86
-0
72
VGA GAIN REGISTER CODE
V
G
A
G
AI
N
(
d
B)
42
36
30
24
18
12
6
0
127
255
383
511
639
767
895
1023
Figure 74. VGA Gain Curve
ADC
The AD9923A uses a high performance ADC architecture
optimized for high speed and low power. Differential nonlin-
earity (DNL) performance is typically better than 1 LSB. The
ADC uses a 2 V input range. See Figure 6 and Figure 8 for
typical linearity and noise performance plots.
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