參數(shù)資料
型號： AD9913BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 27/32頁
文件大?。?/td> 0K
描述： IC DDS 250MSPS 10BIT ADC 32LFCSP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1,500
分辨率（位）： 10 b
主 fclk： 250MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.8V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 帶卷 (TR)
AD9913
Rev. A | Page 4 of 32
Parameter
Conditions/Comments
Min
Typ
Max
Unit
MISCELLANEOUS TIMING CHARACTERISTICS
Wake-Up Time1
Fast Recovery Mode
1
SYSCLK cycles2
Full Sleep Mode
60
μs
Reset Pulse Width High
5
SYSCLK cycles
DATA LATENCY (PIPELINE DELAY)
Frequency, Phase-to-DAC Output
Matched latency enabled
11
SYSCLK cycles
Frequency-to-DAC Output
Matched latency disabled
11
SYSCLK cycles
Phase-to-DAC Output
Matched latency disabled
10
SYSCLK cycles
Delta Tuning Word-to-DAC Output (Linear Sweep)
14
SYSCLK cycles
CMOS LOGIC INPUTS
Logic 1 Voltage
1.2
V
Logic 0 Voltage
0.4
V
Logic 1 Current
700
+700
nA
Logic 0 Current
700
+700
nA
Input Capacitance
3
pF
CMOS LOGIC OUTPUTS
1 mA load
Logic 1 Voltage
1.5
V
Logic 0 Voltage
0.125
V
POWER SUPPLY CURRENT
DVDD (1.8 V) Pin Current Consumption
46.5
mA
DAC_CLK_AVDD (1.8 V)
4.7
mA
DAC_AVDD (1.8 V) Pin Current Consumption
6.2
mA
PLL_AVDD (1.8 V)
1.8
mA
CLK_AVDD (1.8 V) Pin Current Consumption
4.3
mA
POWER CONSUMPTION
Single Tone Mode
PLL enabled, CMOS input
50
66.5
mW
PLL disabled, differential input
57
70.5
mW
PLL enabled, XTAL input
52
68.5
mW
Modulus Mode
PLL disabled
94.6
mW
Linear Sweep Mode
PLL disabled
98.4
mW
Power-Down
Full
15
mW
Safe
PLL enabled
44.8
mW
PLL Modes
VCO 1
Differential Input Mode
11
mW
CMOS Input Mode
7.5
mW
Crystal Mode
5.4
mW
VCO 2
Differential Input Mode
15
mW
CMOS Input Mode
11.5
mW
Crystal Mode
9.4
mW
1 Refer to the Power-Down Features section.
2 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier and divider are not used, the
SYSCLK frequency is the same as the external reference clock frequency.
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