參數(shù)資料
型號(hào): AD9913BCPZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 19/32頁(yè)
文件大?。?/td> 0K
描述: IC DDS 250MSPS 10BIT ADC 32LFCSP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝: 1,500
分辨率(位): 10 b
主 fclk: 250MHz
調(diào)節(jié)字寬(位): 32 b
電源電壓: 1.8V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 帶卷 (TR)
AD9913
Rev. A | Page 26 of 32
REGISTER MAP AND BIT DESCRIPTIONS
REGISTER MAP
Note that the highest number found in the Serial Bit Range column for each register in the following tables is the MSB and the lowest
number is the LSB for that register.
Table 9. Control Registers
Register
Name
(Serial
Address)
[Serial Bit
Range]/
Parallel
Address
MSB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
LSB
Bit 0
Default
Value
CFR1—
Control
Function
Register 1
(0x00)
[7:0]/0x00
External
Power-
Down
Mode
Digital
Power-
Down
DAC
Power-
Down
Clock
Input
Power-
Down
Load SRR @
IO_UPDATE
Autoclear
Auxiliary
Accum.
Autoclear
Phase
Accum.
Enable
Sine
Output
0x00
[15:8]/0x01
Clear
Auxiliary
Accum.
Clear
Phase
Accum.
Destination [1:0]
00: Frequency Word
01: Phase Word
Auxiliary
Accumulator
Enable
DC
Output
Active
Linear
Sweep
State
Trigger
Active
Linear
Sweep
No-Dwell
Active
0x00
[23:16]/0x02
LSB First
Internal Profile Control [2:0]
Sync Clock
Disable
Open
Direct
Switch
Mode
Active
0x00
[31:24]/0x03
Open
Modulus
Enable
Use Internal
Profile
Match
Pipe
Delays
Active
Open
0x00
CFR2—
Control
Function
Register 2
(0x01)
[7:0]/0x04
CMOS
Clock
Crystal
Clock
PLL
Power-
PLL LO
Range
PLL Input
Div by 2
VCO2 Sel
PLL Reset
PLL Lock
0x32
[15:8]/0x05
PLL
Output
Div by 2
PLL Multiplication Factor [5:0]
Open
0x14
DAC Control
Register
(0x02)
[7:0]/0x06
FS C [7:0]
0xFF
[15:8]/0x07
Open
Reserved
Open
FSC [9:8]
0x13
[23:16]/0x08
Reserved
0x7F
[31:24]/0x09
Reserved
0x00
FTW
(0x03)
[7:0]/0x0A
Frequency Tuning Word [7:0]
0x00
[15:8]/0x0B
Frequency Tuning Word [15:8]
0x00
[23:16]/0x0C
Frequency Tuning Word [23:16]
0x00
[31:24]/0x0D
Frequency Tuning Word [31:24]
0x00
POW
(0x04)
[7:0]/0x0E
Phase Offset Word [7:0]
0x00
[15:8]/0x0F
Open [1:0]
Phase Offset Word [13:8]
0x00
Linear Sweep
Parameter
Register
(0x06)
[7:0]/0x12
Sweep Parameter Word 0 [7:0]
0x00
[15:8]/0x13
Sweep Parameter Word 0 [15:8]
0x00
[23:16]/0x14
Sweep Parameter Word 0 [23:16]
0x00
[31:24]/0x15
Sweep Parameter Word 0 [31:24]
0x00
[39:32]/0x16
Sweep Parameter Word 1 [7:0]
0x00
[47:40]/0x17
Sweep Parameter Word 1 [15:8]
0x00
[55:48]/0x18
Sweep Parameter Word 1 [23:16]
0x00
[63:56]/0x19
Sweep Parameter Word 1 [31:24]
0x00
Linear Sweep
Delta
Parameter
Register
(0x07)
[7:0]/0x1A
Rising Delta Word [7:0]
0x00
[15:8]/0x1B
Rising Delta Word [15:8]
0x00
[23:16]/0x1C
Rising Delta Word [23:16]
0x00
[31:24]/0x1D
Rising Delta Word [31:24]
0x00
[39:32]/0x1E
Falling Delta Word [7:0]
0x00
[47:40]/0x1F
Falling Delta Word [15:8]
0x00
[55:48]/0x20
Falling Delta Word [23:16]
0x00
[63:56]/0x21
Falling Delta Word [31:24]
0x00
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