AVDD (1.8 V), DVDD (1.8 V), and DVDD_I/O = 1.8 V ± 5%, T = 25°C" />
參數(shù)資料
型號： AD9913BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 23/32頁
文件大?。?/td> 0K
描述： IC DDS 250MSPS 10BIT ADC 32LFCSP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1,500
分辨率（位）： 10 b
主 fclk： 250MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.8V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 帶卷 (TR)
AD9913
Rev. A | Page 3 of 32
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
AVDD (1.8 V), DVDD (1.8 V), and DVDD_I/O = 1.8 V ± 5%, T = 25°C, RSET = 4.64 kΩ, DAC full-scale current = 2 mA, external
reference clock frequency = 250 MHz with REF_CLK multiplier disabled, unless otherwise noted.
Table 1.
Parameter
Conditions/Comments
Min
Typ
Max
Unit
REF_CLK INPUT CHARACTERISTICS
Frequency Range
REF_CLK Multiplier
Disabled
250
MHz
Enabled
250
MHz
REF_CLK Input Divider Frequency
Full temperature range
83
MHz
VCO Oscillation Frequency
VCO1
16
250
MHz
VCO2
100
250
MHz
PLL Lock Time
25 MHz reference clock, 10× PLL
60
μs
External Crystal Mode
25
MHz
CMOS Mode
VIH
0.9
V
VIL
0.65
V
Input Capacitance
3
pF
Input Impedance (Differential)
2.7
kΩ
Input Impedance (Single-Ended)
1.35
kΩ
Duty Cycle
45
55
%
REF_CLK Input Level
355
1000
mV p-p
DAC OUTPUT CHARACTERISTICS
Full-Scale Output Current
4.6
mA
Gain Error
14
6
%FS
Output Offset
+0.1
μA
Differential Nonlinearity
0.4
+0.4
LSB
Integral Nonlinearity
0.5
+0.5
LSB
AC Voltage Compliance Range
±400
mV
SPURIOUS-FREE DYNAMIC RANGE
Refer to Figure 6
SERIAL PORT TIMING CHARACTERISTICS
SCLK Frequency
32
MHz
SCLK Pulse Width
Low
17.5
ns
High
3.5
ns
SCLK Rise/Fall Time
2
ns
Data Setup Time to SCLK
5.5
ns
Data Hold Time to SCLK
0
ns
Data Valid Time in Read Mode
22
ns
PARALLEL PORT TIMING CHARACTERISTICS
PCLK Frequency
33
MHz
PCLK Pulse Width
Low
10
ns
High
20
ns
PCLK Rise/Fall Time
2
ns
Address/Data Setup Time to PCLK
3.0
ns
Address/Data Hold Time to PCLK
0.3
ns
Data Valid Time in Read Mode
8
ns
IO_UPDATE/PROFILE(2:0) TIMING
Setup Time to SYNC_CLK
0.5
ns
Hold Time to SYNC_CLK
1
SYNC_CLK cycles
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