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參數(shù)資料
| 型號(hào)： | AD9913BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS 250MSPS 10BIT ADC 32LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 250MHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.8V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
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AD9913
Rev. A | Page 30 of 32
Control Function Register 2 (CFR2)
Address 0x01; 2 bytes are assigned to this register.
Table 11. Bit Descriptions for CFR2
Bit(s)
Bit Name
Description
15
PLL Output Div by 2
See Table 7 for details on multiplication factor configuration.
14:9
PLL Multiplication Factor
8
Open
Leave this bit at the default state.
7
CMOS Clock Mode
See Table 6 for directions on programming this bit.
6
Crystal Clock Mode
See Table 6 for directions on programming this bit.
5
PLL Power-Down
0 = PLL is active
1 = PLL is inactive and in its lowest power state
4
PLL LO Range
0 = use this setting for PLL if the PLL reference frequency is >5 MHz.
1 = use this setting for PLL if the PLL reference frequency is <5 MHz.
3
PLL Input Div by 2
0 = the PLL reference frequency = the REF_CLK input frequency.
1 = the PLL reference frequency = the REF_CLK input frequency.
2
VCO2 Sel
0 = use this setting for VCO frequencies below 100 MHz and/or to optimize for power rather
than performance.
1 = use this setting to optimize for performance; this setting results in slightly higher power
consumption. Note: When setting this bit, an IO_UPDATE must occur within 40
μs of the PLL
power-down bit (CFR2 [5]) going low.
1
PLL Reset
0 = the PLL logic is reset and non-operational until this bit is set.
1 = the PLL logic operates normally.
0
PLL Lock
This read-only bit is set when the REF_CLK PLL is locked.
DAC Control Register
Address 0x02; 4 bytes are assigned to this register.
Table 12. Bit Descriptions for DAC Control Register
Bit(s)
Bit Name
Description
15:14, 10
Open
Leave these bits at their default state.
9:0
FSC
This 10-bit number controls the full-scale output current of the DAC.
31:16,13:11
Reserved
Leave these bits at their default state.
Frequency Tuning Word Register (FTW)
Address 0x03, 4 bytes are assigned to this register.
Table 13. Bit Descriptions for FTW Register
Bit(s)
Bit Name
Description
31:0
Frequency Tuning Word
32-bit frequency tuning word.
Phase Offset Word Register (POW)
Address 0x04, 2 bytes are assigned to this register.
Table 14. Bit Descriptions for POW Register
Bit(s)
Bit Name
Description
15:14
Open
Leave these bits at their default state.
13:0
Phase Offset Word
14-bit phase offset word.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9913BCPZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
| AD9914 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3.5 GSPS Direct Digital Synthesizer with 12-Bit DAC |
| AD9914/PCBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 3.5 GSPS DDS w/Upconverter eval bd. RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| AD9914BCPZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC - 多種 3.5 GSPS DDS w/Upconverter RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 分辨率:8 bit 工作電源電壓:2.7 V to 5.5 V 功耗: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:MSOP-10 封裝:Reel |
| AD9914BCPZ-REEL7 | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC - 多種 3.5 GSPS DDS w/Upconverter RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 分辨率:8 bit 工作電源電壓:2.7 V to 5.5 V 功耗: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:MSOP-10 封裝:Reel |
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