參數(shù)資料
型號: AD9913BCPZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 25/32頁
文件大?。?/td> 0K
描述: IC DDS 250MSPS 10BIT ADC 32LFCSP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準包裝: 1,500
分辨率(位): 10 b
主 fclk: 250MHz
調(diào)節(jié)字寬(位): 32 b
電源電壓: 1.8V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 帶卷 (TR)
AD9913
Rev. A | Page 31 of 32
Linear Sweep Parameter Register
Address 0x06, 8 bytes are assigned to this register. This register is only effective if CFR1 [11] or CFR1 [28] are set. See the Auxiliary
Accumulator section.
Table 15. Bit Descriptions for Linear Sweep Limit Register
Bit(s)
Bit Name
Description
63:32
Sweep Parameter Word 1
32-bit linear sweep upper limit value. In programmable modulus mode, these bits are used
to set the B value found in the AN-953 Application Note.
31:0
Sweep Parameter Word 0
32-bit linear sweep lower limit value. In programmable modulus mode, these bits are used
to set the X value found in the AN-953 Application Note.
Linear Sweep Delta Parameter Register
Address 0x07, 8 bytes are assigned to this register. This register is only effective if CFR1 [11] or CFR1 [28] are set. See the Auxiliary
Accumulator section.
Table 16. Bit Descriptions for Linear Sweep Step Size Register
Bit(s)
Bit Name
Description
63:32
Falling Delta Word
32-bit linear sweep decrement step size value.
31:0
Rising Delta Word
32-bit linear sweep increment step size value. In programmable modulus mode, these bits
are used to set the A value found in the AN-953 Application Note.
Linear Sweep Ramp Rate Register
Address 0x08, 4 bytes are assigned to this register. This register is only effective if CFR1 [11] or CFR1 [28] are set. See the Auxiliary
Accumulator section.
Table 17. Bit Descriptions for Linear Sweep Rate Register
Bit(s)
Bit Name
Description
31:16
Falling Sweep Ramp Rate
16-bit linear sweep negative slope value that defines the time interval between decrement
values.
15:0
Rising Sweep Ramp Rate
16-bit linear sweep positive slope value that defines the time interval between increment
values.
Profile Registers
There are eight consecutive serial I/O addresses dedicated to device profiles. In normal operation, the active profile register is selected
using the external profile select pins.
Profile 0 to Profile 7—Single Tone Register
Address 0x09 to Address 0x10, 6 bytes are assigned to these registers.
Table 18. Bit Descriptions for Profile 0 to Profile 7 Single Tone Register
Bit(s)
Bit Name
Description
47:46
Open
Leave these bits at their default state.
45:32
Phase Offset Word
This 14-bit number controls the DDS phase offset.
31:0
Frequency Tuning Word
This 32-bit number controls the DDS frequency.
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